1151 1.0

SATA Device Controller on Altera Arria II GX The LDS SATA DEVICE AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The...

1152 1.0

SATA HOST Controller on Cyclone IV GX The LDS SATA HOST C4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Cyclone IV GX FPGA. The ...

1153 1.0

SATA Device on Stratix IV GX The LDS SATA DEVICE STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA STRATIX IV GX FPGA. ...

1154 1.0

SATA Device on Virtex 6 The LDS SATA DEVICE XV6 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA D...

1155 1.0

SATA RECORDER ON VIRTEX 6 The LDS SATA RECORDER XV6 IP is a complete recorder system IP. It can be configured according the recording performance required and the quantity of ...

1156 0.0

FPGA Proven PCIe GEN6 Controller PCIe GEN6 Controller IP Delivers data speed up to 64GT/s (Gigatransfers per second) per lane. Multi-channel packet processing and enhanced RAS capabil...

1157 0.0

PCIe GEN6 PHY Designed for next-generation PCIe systems, the PCIe GEN6 PHY IP supports data rates up to 64GT/s per lane with advanced PAM4 signaling. It ensures eff...

1158 10.0

USB 3.2 Gen2/Gen1 PHY IP in TSMC(3nm, 5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm) M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps. It is compl...

1159 0.0

USB 2.0/1.1 PHY (6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm) USB 2.0 PHY M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power consumptio...

1160 5.0

M31 DisplayPort RX IP in 6/7nm, 22nm M31 DisplayPort RX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort RX supp...

1161 20.0

MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and 55nm) MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pi...

1162 5.0

M31 eUSB2 PHY IP(2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 28nm) Embedded USB2 (eUSB2) is a new generation specification proposed by USB Association that extends USB 2.0 specification and uses 1.2V/1.0V as the inter...

1163 10.0

UniPro Controller 2.0 IP (host / device) The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...

1164 10.0

UniPro 1.6 Host/Device IP The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...

1165 0.0

MIPI D-PHY Universal IP The MXL-PHY-MIPI is a high-frequency low-power, low cost, source-synchronous, physical Layer compliant with the MIPI Alliance Standard for D-PHY. Alth...

1166 0.0

MIPI D-PHY CSI-2 RX (Receiver) IP The MXL-PHY-CSI-2-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ...

1167 10.0

AXI QSPI with Execute in Place The Quad Serial Peripheral Interface module either controls a serial data link as a master, or reacts to a serial data link as a slave. The IPC...

1168 0.0

MIPI M-PHY Compliant (HS-G2) IP The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be used...

1169 0.0

MIPI M-PHY DigRF Compliant IP The MXL-M-PHY-DIGRF is a high frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY and DigRF. The IP c...

1170 0.0

MIPI D-PHY DSI TX (Transmitter) IP The MXL-DPHY-DSI-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ...

1171 0.0

MIPI D-PHY DSI RX (Receiver) IP The MXL-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ...

1172 0.0

MIPI D-PHY CSI-2 TX (Transmitter) IP The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY....

1173 102.0

MIPI C-PHY/D-PHY Combo CSI-2 RX IP 4.5Gsps/4.5Gbps in TSMC N7 The MXL-CDPHY-4p5G-CSI-2-RX-T-N7FF is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specific...

1174 0.0

MIPI D-PHY 4-Lane CSI2-TX (Transmitter) in TowerJazz 65nm The MXL-DPHY-CSI-2-TX-4L-TW-065ISC is a high-frequency low-power, low-cost, sourcesynchronous, Physical Layer supporting the MIPI Alliance Standard fo...

1175 11.0

MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 22ULL The MXL-DPHY-CSI-2-TX+-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification...

1176 11.0

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+ The MXL-DPHY-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification...

1177 11.0

MIPI D-PHY DSI RX (Receiver/Peripheral) in UMC 22ULP/22ULL The MXL-DPHY-DSI-RX-U-22ULP-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificat...

1178 50.0

AHB Octal SPI Controller with PSRAM and XIP Support The Silvaco Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, usually an ind...

1179 52.0

MIPI D-PHY DSI RX (Receiver) in GlobalFoundries 22FDX The MXL-DPHY-DSI-RX-GF-22FDX is a high-frequency, low-power, low-cost, source-synchronous, physical layer supporting the MIPI Alliance Specification f...

1180 11.0

MIPI C-PHY/D-PHY Combo 2-Lane CSI-2 TX+ IP in TSMC 40ULP The MXL-CDPHY-2L-CSI-2-TX+-40ULP is a high-frequency, low-power, low-cost, sourcesynchronous, physical Layer supporting the MIPI Alliance Specificatio...

1181 11.0

MIPI D-PHY Universal IP in UMC 28HPC+ The MXL-DPHY-UNIV-U-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for...

1182 52.0

MIPI C-PHY/D-PHY Combo DSI RX+ IP (4.5Gsps/trio, 6.5Gbps/lane) in TSMC 16FFC The MXL-CD-PHY-DSIRX+-T-16FFC is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...

1183 11.0

MIPI C-PHY DSI TX (Transmitter/Host) IP in TSMC 22ULL The MXL-CPHY-2p5G-DSI-TX-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificati...

1184 40.0

RapidIO Controller with V4.1 Support Mobiveil's RapidIO Controller solution (GRIO) is a highly flexible and configurable IP. The Mobiveil RapidIO Controller Solution can be used as a Host...

1185 30.0

RapidIO to AXI Bridge (RAB) Mobiveil's RapidIO-AXI Bridge (RIO-AXI Bridge) is a highly flexible and configurable IP used along with Mobiveil native RapidIO Controller (GRIO) to p...

1186 40.0

CXL 2.0 Agilex FPGA Acclerator Card Mobiveil’s CXL-Aglx Accelerator platform is a PCIe® Gen5 add-in card with latest Intel’s Agilex I series FPGA. It supports High-Performance Applicatio...

1187 50.0

PCIe Gen3 to SRIO Gen3 Bridge (FPGA) Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Expre...

1188 10.0

USB-C 3.0 femtoPHY in Type-C in TSMC (28nm, 16nm, 12nm) The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer a...

1189 0.0

AXI Interconnect Fabric The AXI Interconnect provides the necessary infrastructure to connect as many as 8 shared AXI Slaves to as many as 4 AXI Bus Masters. AXI defines 5...

1190 4.0

I2C Master Controller The ntI2C_M is an I2C-bus multi-master interface controller and provides a cost-effective solution for a wide range of applications that require a low...

1191 0.0

CXL 3.0 Host Controller CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...

1192 0.0

PCIE Gen6 digital controller (Root Complex) PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE sp...

1193 0.0

PCIE Gen6 digital controller (Dual Mode) PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE sp...

1194 0.0

CXL 3.0 Device Controller CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...

1195 0.0

PCIe Gen6.0 Retimer Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...

1196 0.0

CXL 3.0 Retimer Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...

1197 0.0

AXI to AHB Lite Bus Bridge The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...

1198 0.0

CXL 2.0 Retimer Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...

1199 0.0

UCIE 1.0 Support for multiple protocol PCIE/CXL/Streaming...

1200 0.0

PCIE Gen7 Controller Gen7 supports 128Gbps and backward compatible with previous versions of PCIE....