Design & Reuse
Catalog of SIP Cores
System on Chip design resources
1944 IP
1201
0.0
PCIe 6.2 Switch IP Controller
...
1202
6.5077
MIPI D-PHY TRx 2.5Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
1203
6.5077
MIPI D-PHY TRx 2.5Gbps (28nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
1204
5.5077
DSC 1.2b Encoder
The DSC 1.2b Encoder is an efficient video compression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for lo...
1205
5.5077
DSC 1.2b Decoder
The DSC 1.2b Decoder is an efficient video decompression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for ...
1206
6.5077
MIPI CSI-2 RX Controller
The Camera Serial Interface 2 (CSI-2) Receiver (RX) Controller is a digital core that implements all protocol functions defined in the MIPI Alliance S...
1207
6.5077
MIPI DSI-2 TX Controller
The Display Serial Interface 2 (DSI-2) Transmitter (TX) Controller is a digital core that implements all protocol functions defined in the MIPI Allian...
1208
0.0
AXI to APB Bus Bridge
The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction. This is accomplished via two state machines – one ...
1209
6.5077
MIPI C-PHY TRx 8Gsps (5nm)
The MIPI C-PHY IP supports data rates of up to 8Gsps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provides...
1210
4.5077
PCIe refclk buffer (14nm)
The output buffer to deliver a differential clock signal from inside chip to outside for PCIe interface...
1211
4.5077
PCIe refclk buffer (8nm)
The output buffer to deliver a differential clock signal from inside chip to outside for PCIe interface...
1212
9.5077
PCIe 6.0 PHY (4nm)
The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 6.0 specification. This IP offers a cost-effective and low-power so...
1213
8.5077
PCIe 4.0 PHY (8nm)
The PCIe PHY IP consists of hardmacro PMA and softmacro PCS compliant to PCIe Base 4.0 specification. This IP offers a cost-effective and low-power so...
1214
5.5077
eDP v1.5a RX PHY (14nm)
The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...
1215
6.5077
MIPI C-PHY TRx(80-8000Msps) / MIPI D-PHY TRx(80-9000Mbps) Combo PHY (4nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 9Gbps for D-PHY and 8Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Es...
1216
6.5077
MIPI D-PHY TRx 4.5Gbps (8nm)
The MIPI D-PHY IP supports data rates of up to 4.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
1217
6.5077
MIPI D-PHY TRx 4.5Gbps (5nm)
The MIPI D-PHY IP supports data rates of up to 4.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
1218
6.5077
MIPI D-PHY TRx 2.5Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
1219
6.5077
MIPI D-PHY TRx 2.5Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
1220
6.5077
MIPI D-PHY TRx 2.5Gbps (11nm)
The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
1221
5.5077
MIPI D-PHY TRx 2.1Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
1222
6.5077
MIPI D-PHY TRx 2.1Gbps (14nm)
The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...
1223
5.5077
MIPI D-PHY TRx 2.15Gbps (28nm)
The MIPI D-PHY IP supports data rates of up to 2.15Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provi...
1224
6.5077
MIPI C-PHY TRx 2.5Gsps / D-PHY TRx 4.5Gbps Combo PHY (8nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...
1225
6.5077
MIPI C-PHY TRx 2.5Gsps / D-PHY TRx 4.5Gbps Combo PHY (4nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...
1226
180.0
MIPI CSI-2 Controller Core V2
The Rambus CSI-2 Controller Core V2 is the second generation CSI-2 controller core. It is further optimized for high performance, low power and small ...
1227
10.0
AHB Multi Fabric
The AHB Fabric provides the necessary infrastructure to connect up to 16 shared AHB Slaves to up to 16 AHB-Lite Bus Masters. The off-the-self configu...
1228
180.0
MIPI DSI-2 Controller Core
The Rambus DSI-2 Controller Core is the second generation DSI controller core. It is further optimized for high performance, low power and small size....
1229
0.0
MIPI Testbench
Rambus MIPI Testbench from Rambus emulates a MIPI device enabling end-to-end simulation of a MIPI design. This includes the follow features: • Separ...
1230
0.0
PCIe Controller Testbench
PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design. This includes the following features: • R...
1231
0.0
PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface
Rambus PCIe 3.0 with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 3.0 with AXI is...
1232
0.0
PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
Rambus PCIe 3.0 Controller is a highly configurable PCIe 3.0 interface Soft IP designed for ASIC and FPGA implementations supporting endpoint, root po...
1233
195.0
PCIe 7.0 Retimer Controller
The Rambus PCI Express® (PCIe®) 7.0 Retimer Controller provides a complete digital data path solution that delivers best-in-class latency, power and a...
1234
190.0
PCIe 6.2 Switch
The Rambus PCI Express® (PCIe®) 6.2 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC implementations. It enables the con...
1235
0.0
CXL 3.0 IP
EMPOWER YOUR DESIGN WITH UNMATCHED CXL PERFORMANCE Highly advanced and versatile CXL Controller IP that empowers your design with unparalleled spee...
1236
0.0
Multi-Link Multi-Protocol SerDes 16Gbps in TSMC 28HPC
Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...
1237
0.0
AHB Channel with Decoder and Data Mux
The AHB Channel provides the necessary infrastructure to connect as many as 7 AHB Slaves (numbered 1-7) to an AHB bus Master. The AHB Channel perform...
1238
0.0
DisplayPort Transmitter Link Controller
Our 5th generation DisplayPort Transmitter Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link r...
1239
0.0
DisplayPort Receiver Link Controller
Our 5th generation DisplayPort Receiver Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link rate...
1240
25.0
Flash SPI controller master/slave
Veriest's SPI Master Controller IP provides an industry standard data communication channel between the AMBA APB and SPI buses. It supports SPI master...
1241
1.0
SMIC 0.18um PCI-X IO
The PCI-X transceiver is a IP version of PCI-X I/O pads, which is fully compatible with PCI-X R1.0 specification....
1242
1.0
USB1.1 PHY-SMIC15_USB11_01
The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed...
1243
1.0
USB 1.1 PHY-SMIC18_USB11_01_L
The USB1.1 PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB1.1 core with RCV, VM and VP. It is desig...
1244
1.0
USB1.1 PHY-SMIC25_USB11_01
The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed...
1245
1.0
USB1.1 PHY-SMIC25_USB11_02
The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed...
1246
1.0
USB 1.1 PHY-GSMC15_USB11_01_L
The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed...
1247
1.0
GSMC 0.15um 1.2V/3.3V PCI I/O Cells
VeriSilicon GSMC 0.15um 1.2V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) ...
1248
0.0
APB Channel with Decoder and Data Mux
The APB Channel provides the necessary infrastructure to connect as many as 16 AHB Slaves (numbered 0-15) to an APB Bus Master. The APB Channel perfo...
1249
1.0
GSMC 0.18um PCI I/O Cells Library
VeriSilicon GSMC 0.18um 1.8V/3.3V PCI I/O Cells Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC)...
1250
1.0
GSMC0.18um PCI I/O Cells DUP Library
VeriSilicon GSMC 0.18um 1.8V/3.3V PCI I/O Cells Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC)...