1201 1.0

Video-by-One Receiver IP_16ch This document introduces the low power Innosilicon Video-by-One (VBO) Receiver IP containing PHY and controller. Innosilicon VBO RX is designed for re...

1202 1.0

Video-by-One Transmitter IP_8ch Innosilicon VBO TX IP is designed for transmitting video data from a video source device to a display device. It is compatible with V-By-One HS 1.4 st...

1203 1.0

LVDS RX PHY & Controller Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...

1204 1.0

LVDS TX Combo TTL PHY Innosilicon LVDS implements LVDS TIA/EIA protocol. Normally, Innosilicon LVDS contains four 7-bit parallel-load serial-out shift registers, a 7X clock...

1205 1.0

LVDS TX PHY & Controller Innosilicon LVDS implements LVDS TIA/EIA protocol. It specifies a low-voltage point-to-point signal interface, which uses a differential driver connec...

1206 1.0

V-By-One PHY & Controller (Tx+ Rx) INNOSILICON™ VBO IP is designed for transmitting or receiving video signals between a video source device and display device, The IP is fully complian...

1207 2.5

I2C MAster Slave The MI2CMS macro implements a synchronous single-chip I2C Master and Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus...

1208 2.5

I2C Master The MI2CM macro implements a synchronous single-chip I2C Master only Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is ca...

1209 0.0

AHB Low Power Subsystem - ARM M0 The AHB Low Power Subsystem is an AMBA® based system that is useful as the basic digital infrastructure for building low power SOCs. The subsystem co...

1210 2.5

I2C Slave The MI2CS macro implements a synchronous single-chip I2C Slave Macro capable of linking one CPU to one I2C-bus. Communication with I2C-bus is carried ...

1211 2.5

SATA HOST Synchronous IP The LDS SATA HOST XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...

1212 2.5

Serial ATA Dual Host Controller The LDS_SATA HOST DUAL XV5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XV5...

1213 2.5

SATA Host controller on Virtex 5 FXT The LDS SATA HOST XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST XV5 IP is com...

1214 2.5

Dual SATA Host controller on Virtex 5 FXT FPGA The LDS SATA HOST DUAL XF5 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 5 FPGA. The LDS SATA HOST DUAL XF5...

1215 2.5

SATA Host Controller The LDS SATA HOST STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Startix IV GX FPGA. Th...

1216 2.5

SATA Host Controller on Spartan 6 LXT FPGA The LDS SATA HOST SP6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Spartan 6 FPGA. The LDS SATA HOST SP6 IP is co...

1217 2.5

SATA Host Controller on Virtex 6 LXT The LDS SATA HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA HOST XV6 IP is com...

1218 2.5

SATA III HOST Controller on Virtex 6 The LDS SATA 3 HOST XV6 IP incorporates the Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 speed grade 2 FPGA. The LDS SATA 3 ...

1219 2.5

SATA Host on Altera Arria II GX The LDS SATA HOST AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The L...

1220 0.0

AHB Performance Subsystem - ARM M3 The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional per...

1221 2.5

SATA Device Controller on Altera Arria II GX The LDS SATA DEVICE AR2GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA ARRIA II GX FPGA. The...

1222 2.5

SATA HOST Controller on Cyclone IV GX The LDS SATA HOST C4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA Cyclone IV GX FPGA. The ...

1223 2.5

SATA Device on Stratix IV GX The LDS SATA DEVICE STR4GX IP incorporates the Transport layer, the Link layer, the PHY layer and the Rate Macth FIFO on a ALTERA STRATIX IV GX FPGA. ...

1224 2.5

SATA Device on Virtex 6 The LDS SATA DEVICE XV6 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Virtex 6 FPGA. The LDS SATA D...

1225 2.5

SATA RECORDER ON VIRTEX 6 The LDS SATA RECORDER XV6 IP is a complete recorder system IP. It can be configured according the recording performance required and the quantity of ...

1226 0.0

FPGA Proven PCIe GEN6 Controller PCIe GEN6 Controller IP Delivers data speed up to 64GT/s (Gigatransfers per second) per lane. Multi-channel packet processing and enhanced RAS capabil...

1227 0.0

PCIe GEN6 PHY Designed for next-generation PCIe systems, the PCIe GEN6 PHY IP supports data rates up to 64GT/s per lane with advanced PAM4 signaling. It ensures eff...

1228 0.0

CXL 3 Controller The CXL 3 Controller IP is forward compatible with CXL 3.x and backward compatible with previous versions, offering flexible configurations needed for...

1229 20.0

USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm) M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps. It is compl...

1230 0.0

USB 2.0/1.1 PHY (6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm) USB 2.0 PHY M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power consumptio...

1231 0.0

AXI Performance Subsystem The AXI Performance Subsystem is an AMBA® AXI4 based system that is useful as the digital infrastructure for building SOCs needing high performance. ...

1232 10.0

M31 DisplayPort RX IP in 6/7nm,12/16nm, 22nm M31 DisplayPort RX IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications. DisplayPort RX supp...

1233 20.0

MIPI M-PHY v4.1/v3.1 IP in TSMC(5nm, 6nm, 7nm, 12nm,16nm, 22nm, 28nm, 40nm, and 55nm) MIPI M-PHY is a serial interface technology with high bandwidth capabilities, which is particularly developed for mobile applications to obtain low pi...

1234 10.0

M31 eUSB2 PHY IP(2nm, 3nm, 4nm, 5nm, 6nm, 7nm, 28nm) Embedded USB2 (eUSB2) is a new generation specification proposed by USB Association that extends USB 2.0 specification and uses 1.2V/1.0V as the inter...

1235 10.0

UniPro 2.0 Host/Device IP The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...

1236 10.0

UniPro 1.6 Host/Device IP The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...

1237 5.0

Power Management IC - I3C Basic Interface IP Power Management IC (PMIC) is designed for DDR5 RDIMM, DDR5 LRDIMM, DDR5 NVDIMM application. PMIC is used for switching and LDO regulators. PMIC-I3C I...

1238 5.0

MIPI SPMI Host Controller The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor s...

1239 0.0

MIPI D-PHY Universal IP The MXL-PHY-MIPI is a high-frequency low-power, low cost, source-synchronous, physical Layer compliant with the MIPI Alliance Standard for D-PHY. Alth...

1240 0.0

MIPI D-PHY CSI-2 RX (Receiver) IP The MXL-PHY-CSI-2-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ...

1241 10.0

AXI QSPI with Execute in Place The Quad Serial Peripheral Interface module either controls a serial data link as a master, or reacts to a serial data link as a slave. The IPC...

1242 0.0

MIPI M-PHY Compliant (HS-G2) IP The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be used...

1243 0.0

MIPI M-PHY DigRF Compliant IP The MXL-M-PHY-DIGRF is a high frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY and DigRF. The IP c...

1244 0.0

MIPI D-PHY DSI TX (Transmitter) IP The MXL-DPHY-DSI-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ...

1245 0.0

MIPI D-PHY DSI RX (Receiver) IP The MXL-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ...

1246 0.0

MIPI D-PHY CSI-2 TX (Transmitter) IP The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY....

1247 65.0

MIPI C-PHY/D-PHY Combo RX IP 4.5Gsps/4.5Gbps in TSMC N7 The MXL-CDPHY-4p5G-CSI-2-RX-T-N7FF is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specific...

1248 25.0

MIPI D-PHY 4-Lane CSI2-TX (Transmitter) in TowerJazz 65nm The MXL-DPHY-0p2G-CSI-2-TX-T-180BCD is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard ...

1249 40.0

MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 22ULL The MXL-DPHY-CSI-2-TX+-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification...

1250 0.0

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+ The MXL-DPHY-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification...