1201 10.0

UniPro Controller 2.0 IP (host / device) The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...

1202 10.0

UniPro 1.6 Host/Device IP The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...

1203 5.0

MIPI SPMI Host Controller The System Power Management Interface is a two wire interface that connects the integrated power controller (PC) of a System-on-Chip (SoC) processor s...

1204 0.0

MIPI D-PHY Universal IP The MXL-PHY-MIPI is a high-frequency low-power, low cost, source-synchronous, physical Layer compliant with the MIPI Alliance Standard for D-PHY. Alth...

1205 0.0

MIPI D-PHY CSI-2 RX (Receiver) IP The MXL-PHY-CSI-2-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ...

1206 10.0

AXI QSPI with Execute in Place The Quad Serial Peripheral Interface module either controls a serial data link as a master, or reacts to a serial data link as a slave. The IPC...

1207 0.0

MIPI M-PHY Compliant (HS-G2) IP The MXL-M-PHY-MIPI is a high-frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY. The IP can be used...

1208 0.0

MIPI M-PHY DigRF Compliant IP The MXL-M-PHY-DIGRF is a high frequency low-power, low-cost, Physical Layer IP compliant with the MIPI Alliance Standard for M-PHY and DigRF. The IP c...

1209 0.0

MIPI D-PHY DSI TX (Transmitter) IP The MXL-DPHY-DSI-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ...

1210 0.0

MIPI D-PHY DSI RX (Receiver) IP The MXL-DPHY-DSI-RX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY. ...

1211 0.0

MIPI D-PHY CSI-2 TX (Transmitter) IP The MXL-DPHY-CSI-2-TX is a high-frequency low-power, low-cost, source-synchronous, Physical Layer compliant with the MIPI Alliance Standard for D-PHY....

1212 102.0

MIPI C-PHY/D-PHY Combo RX IP 4.5Gsps/4.5Gbps in TSMC N7 The MXL-CDPHY-4p5G-CSI-2-RX-T-N7FF is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specific...

1213 0.0

MIPI D-PHY 4-Lane CSI2-TX (Transmitter) in TowerJazz 65nm The MXL-DPHY-0p2G-CSI-2-TX-T-180BCD is a high-frequency low-power, low-cost, source-synchronous, Physical Layer supporting the MIPI Alliance Standard ...

1214 11.0

MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 22ULL The MXL-DPHY-CSI-2-TX+-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification...

1215 11.0

MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+ The MXL-DPHY-CSI-2-TX-T-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification...

1216 11.0

MIPI D-PHY DSI RX (Receiver/Peripheral) in UMC 22ULP/22ULL The MXL-DPHY-DSI-RX-U-22ULP-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificat...

1217 50.0

AHB Octal SPI Controller with PSRAM and XIP Support The Silvaco Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, usually an ind...

1218 52.0

MIPI D-PHY DSI RX (Receiver) in GlobalFoundries 22FDX The MXL-DPHY-DSI-RX-GF-22FDX is a high-frequency, low-power, low-cost, source-synchronous, physical layer supporting the MIPI Alliance Specification f...

1219 11.0

MIPI C-PHY/D-PHY Combo 2-Lane CSI-2 TX+ IP in TSMC 40ULP The MXL-CDPHY-2L-CSI-2-TX+-40ULP is a high-frequency, low-power, low-cost, sourcesynchronous, physical Layer supporting the MIPI Alliance Specificatio...

1220 11.0

MIPI D-PHY Universal IP in UMC 28HPC+ The MXL-DPHY-UNIV-U-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for...

1221 52.0

MIPI C-PHY/D-PHY Combo DSI RX+ IP (4.5Gsps/trio, 6.5Gbps/lane) in TSMC 16FFC The MXL-CD-PHY-DSIRX+-T-16FFC is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...

1222 11.0

MIPI C-PHY DSI TX (Transmitter/Host) IP in TSMC 22ULL The MXL-CPHY-2p5G-DSI-TX-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificati...

1223 40.0

RapidIO Controller with V4.1 Support Mobiveil's RapidIO Controller solution (GRIO) is a highly flexible and configurable IP. The Mobiveil RapidIO Controller Solution can be used as a Host...

1224 30.0

RapidIO to AXI Bridge (RAB) Mobiveil's RapidIO-AXI Bridge (RIO-AXI Bridge) is a highly flexible and configurable IP used along with Mobiveil native RapidIO Controller (GRIO) to p...

1225 75.0

CXL 2.0 Agilex FPGA Acclerator Card Mobiveil’s CXL-Aglx Accelerator platform is a PCIe® Gen5 add-in card with latest Intel’s Agilex I series FPGA. It supports High-Performance Applicatio...

1226 50.0

PCIe Gen3 to SRIO Gen3 Bridge (FPGA) Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Expre...

1227 10.0

USB-C 3.0 femtoPHY in Type-C in TSMC (28nm, 16nm, 12nm) The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer a...

1228 0.0

AXI Interconnect Fabric The AXI Interconnect provides the necessary infrastructure to connect as many as 8 shared AXI Slaves to as many as 4 AXI Bus Masters. AXI defines 5...

1229 4.0

I2C Master Controller The ntI2C_M is an I2C-bus multi-master interface controller and provides a cost-effective solution for a wide range of applications that require a low...

1230 10.0

UCIe Die-to-Die Chiplet Controller Introducing OPENEDGES’ Universal Chiplet Interconnect Express (UCIe) Controller IP, OUC, designed to transform the semiconductor landscape with innova...

1231 0.0

CXL 3.0 Host Controller CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...

1232 0.0

PCIE Gen6 digital controller (Root Complex) PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE sp...

1233 0.0

PCIE Gen6 digital controller (Dual Mode) PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE sp...

1234 0.0

CXL 3.0 Device Controller CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...

1235 0.0

PCIe Gen6.0 Retimer Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...

1236 0.0

CXL 3.0 Retimer Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...

1237 0.0

AXI to AHB Lite Bus Bridge The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...

1238 0.0

CXL 2.0 Retimer Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...

1239 0.0

UCIE 1.0 Support for multiple protocol PCIE/CXL/Streaming...

1240 0.0

PCIE Gen7 Controller Gen7 supports 128Gbps and backward compatible with previous versions of PCIE....

1241 0.0

PCIe 6.2 Switch IP Controller ...

1242 2.0

MIPI D-PHY TRx 2.5Gbps (14nm) The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1243 2.0

MIPI D-PHY TRx 2.5Gbps (28nm) The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1244 1.0

DSC 1.2b Encoder The DSC 1.2b Encoder is an efficient video compression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for lo...

1245 1.0

DSC 1.2b Decoder The DSC 1.2b Decoder is an efficient video decompression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for ...

1246 2.0

MIPI CSI-2 RX Controller The Camera Serial Interface 2 (CSI-2) Receiver (RX) Controller is a digital core that implements all protocol functions defined in the MIPI Alliance S...

1247 2.0

MIPI DSI-2 TX Controller The Display Serial Interface 2 (DSI-2) Transmitter (TX) Controller is a digital core that implements all protocol functions defined in the MIPI Allian...

1248 0.0

AXI to APB Bus Bridge The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction. This is accomplished via two state machines – one ...

1249 2.0

MIPI C-PHY TRx 8Gsps (5nm) The MIPI C-PHY IP supports data rates of up to 8Gsps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provides...

1250 0.0

PCIe refclk buffer (14nm) The output buffer to deliver a differential clock signal from inside chip to outside for PCIe interface...