1251 20.0

MIPI D-PHY DSI RX (Receiver/Peripheral) in UMC 22ULP/22ULL The MXL-DPHY-DSI-RX-U-22ULP-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificat...

1252 50.0

AHB Octal SPI Controller with Execute in Place The Octal Serial Peripheral Interface (OSPI) core is a serial data link (SPI) master which controls an external serial FLASH device. Reading and wr...

1253 35.0

MIPI D-PHY DSI RX (Receiver) in GlobalFoundries 22FDX The MXL-DPHY-DSI-RX-GF-22FDX is a high-frequency, low-power, low-cost, source-synchronous, physical layer supporting the MIPI Alliance Specification f...

1254 10.0

MIPI C-PHY/D-PHY Combo 2-Lane CSI-2 TX+ IP in TSMC 40ULP The MXL-CDPHY-2L-CSI-2-TX+-40ULP is a high-frequency, low-power, low-cost, sourcesynchronous, physical Layer supporting the MIPI Alliance Specificatio...

1255 30.0

MIPI D-PHY Universal IP in UMC 28HPC+ The MXL-DPHY-UNIV-U-28HPC+ is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification for...

1256 0.0

MIPI C-PHY/D-PHY Combo DSI RX+ IP (4.5Gsps/trio, 6.5Gbps/lane) in TSMC 16FFC The MXL-CD-PHY-DSIRX+-T-16FFC is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specification ...

1257 0.0

MIPI C-PHY DSI TX (Transmitter/Host) IP in TSMC 22ULL The MXL-CPHY-2p5G-DSI-TX-T-22ULL is a high-frequency, low-power, low-cost, source-synchronous, physical Layer supporting the MIPI Alliance Specificati...

1258 40.0

RapidIO Controller with V4.1 Support Mobiveil's RapidIO Controller solution (GRIO) is a highly flexible and configurable IP. The Mobiveil RapidIO Controller Solution can be used as a Host...

1259 30.0

RapidIO to AXI Bridge (RAB) Mobiveil's RapidIO-AXI Bridge (RIO-AXI Bridge) is a highly flexible and configurable IP used along with Mobiveil native RapidIO Controller (GRIO) to p...

1260 75.0

CXL 2.0 Agilex FPGA Acclerator Card Mobiveil’s CXL-Aglx Accelerator platform is a PCIe® Gen5 add-in card with latest Intel’s Agilex I series FPGA. It supports High-Performance Applicatio...

1261 50.0

PCIe Gen3 to SRIO Gen3 Bridge (FPGA) Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Expre...

1262 5.0

USB3.2 Gen2x2 xHCI Host Controller MosChip USB3.x Host softcore is designed for embedded host applications with USB SSP operations and fall back support of SS and USB2 speed modes over ...

1263 10.0

USB-C 3.0 femtoPHY in Type-C in TSMC (28nm, 16nm, 12nm) The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer a...

1264 0.0

AXI Interconnect Fabric The AXI Interconnect provides the necessary infrastructure to connect as many as 8 shared AXI Slaves to as many as 4 AXI Bus Masters. AXI defines 5...

1265 5.0

USB3.2 Retimer Controller MosChip USB3.2 Retimer softcore is designed for use USB Port/Cable Retimer applications with USB SuperSpeedPlus/SuperSpeed link operations The IP has ...

1266 4.0

I2C Master Controller The ntI2C_M is an I2C-bus multi-master interface controller and provides a cost-effective solution for a wide range of applications that require a low...

1267 25.0

LPDDR5X/5/4X/4 Memory Controller IP OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

1268 10.0

UCIe Die-to-Die Chiplet Controller Introducing OPENEDGES’ Universal Chiplet Interconnect Express (UCIe) Controller IP, OUC, designed to transform the semiconductor landscape with innova...

1269 0.0

CXL 3.0 Host Controller CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...

1270 0.0

PCIE Gen6 digital controller (Root Complex) PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE sp...

1271 0.0

PCIE Gen6 digital controller (Dual Mode) PCIE is a layered protocol high speed interconnect interface supporting speeds up to 64GT/S and multi lanes and links. The layers specified in PCIE sp...

1272 0.0

CXL 3.0 Device Controller CXL is high bandwidth, low latency interconnect lies between host processor and memory devices/accelerators or other network interface cards. CXL ca...

1273 0.0

PCIe Gen6.0 Retimer Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...

1274 0.0

CXL 3.0 Retimer Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...

1275 0.0

AXI to AHB Lite Bus Bridge The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...

1276 0.0

CXL 2.0 Retimer Retimer that are Physical Layer protocol aware and that interoperate with any pair of Components with any compliant channel on each side of the Retime...

1277 0.0

UCIE 1.0 Support for multiple protocol PCIE/CXL/Streaming...

1278 0.0

PCIE Gen7 Controller Gen7 supports 128Gbps and backward compatible with previous versions of PCIE....

1279 0.0

PCIe 6.2 Switch IP Controller ...

1280 3.0

MIPI D-PHY TRx 2.5Gbps (14nm) The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1281 3.0

MIPI D-PHY TRx 2.5Gbps (28nm) The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1282 0.0

DSC 1.2b Encoder The DSC 1.2b Encoder is an efficient video compression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for lo...

1283 0.0

DSC 1.2b Decoder The DSC 1.2b Decoder is an efficient video decompression IP that complies with the VESA Display Stream Compression (DSC) 1.2b standard. Optimized for ...

1284 0.0

MIPI CSI-2 RX Controller The Camera Serial Interface 2 (CSI-2) Receiver (RX) Controller is a digital core that implements all protocol functions defined in the MIPI Alliance S...

1285 0.0

MIPI DSI-2 TX Controller The Display Serial Interface 2 (DSI-2) Transmitter (TX) Controller is a digital core that implements all protocol functions defined in the MIPI Allian...

1286 0.0

AXI to APB Bus Bridge The AXI to APB Bridge translates an AXI bus transaction (read or write) to an APB bus transaction. This is accomplished via two state machines – one ...

1287 0.0

MIPI C-PHY TRx(80-8000Msps) 5nm The MIPI C-PHY IP supports data rates of up to 8Gsps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provides...

1288 3.0

PCIe refclk buffer (14nm) The output buffer to deliver a differential clock signal from inside chip to outside for PCIe interface...

1289 3.0

PCIe refclk buffer (8nm) The output buffer to deliver a differential clock signal from inside chip to outside for PCIe interface...

1290 0.0

PCIe 6.0 PHY on 4nm The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 6.0 specification. This IP offers a cost-effective and low-power so...

1291 3.0

PCIe 4.0 PHY (8nm) The PCIe PHY IP consists of hardmacro PMA and softmacro PCS compliant to PCIe Base 4.0 specification. This IP offers a cost-effective and low-power so...

1292 3.0

eDP v1.5a RX PHY (14nm) The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1Gbps), and the general mode supports a maximum data rate of up to 4Gbps. This core IP is...

1293 0.0

MIPI C-PHY TRx(80-8000Msps) / MIPI D-PHY TRx(80-9000Mbps) Combo PHY 4nm The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 9Gbps for D-PHY and 8Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Es...

1294 3.0

MIPI D-PHY TRx 4.5Gbps (8nm) The MIPI D-PHY IP supports data rates of up to 4.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1295 0.0

MIPI D-PHY TRx(80-4500Mbps) 5nm The MIPI D-PHY IP supports data rates of up to 4.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1296 3.0

MIPI D-PHY TRx 2.5Gbps (14nm) The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1297 0.0

AXI External Memory Controller The AXI External Bus Interface (EBI) allows the processor to transmit and receive data to an external device, usually a memory (SRAM, Flash, etc.). Th...

1298 3.0

MIPI D-PHY TRx 2.5Gbps (14nm) The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1299 3.0

MIPI D-PHY TRx 2.5Gbps (11nm) The MIPI D-PHY IP supports data rates of up to 2.5Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1300 3.0

MIPI D-PHY TRx 2.1Gbps (14nm) The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...