1301 3.0

MIPI D-PHY TRx 2.1Gbps (14nm) The MIPI D-PHY IP supports data rates of up to 2.1Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provid...

1302 3.0

MIPI D-PHY TRx 2.15Gbps (28nm) The MIPI D-PHY IP supports data rates of up to 2.15Gbps. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provi...

1303 3.0

MIPI C-PHY TRx 2.5Gsps) / D-PHY TRx 4.5Gbps Combo PHY (8nm) The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...

1304 0.0

MIPI C-PHY TRx(80-2500Msps) / MIPI D-PHY TRx(80-4500Mbps) Combo PHY 4nm The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), an...

1305 3.0

UCIe 1.1 PHY for Standard Package (5nm) The UCI Express Specification Revision 1.1 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, and 16GT/s with a 16-lane co...

1306 3.0

UCIe 2.0 PHY for Advanced Package (4nm) The UCI Express Specification Revision 2.0 supports high-speed serialization and deserialization at 4GT/s, 8GT/s, 12GT/s, 16GT/s, 24GT/s and 32GT/s wi...

1307 200.0

MIPI CSI-2 Controller Core V2 The Rambus CSI-2 Controller Core V2 is the second generation CSI-2 controller core. It is further optimized for high performance, low power and small ...

1308 10.0

AHB MultiMatrix Fabric The AHB Fabric provides the necessary infrastructure to connect up to 16 shared AHB Slaves to up to 16 AHB-Lite Bus Masters. The off-the-self configu...

1309 200.0

MIPI DSI-2 Controller Core The Rambus DSI-2 Controller Core is the second generation DSI controller core. It is further optimized for high performance, low power and small size....

1310 0.0

MIPI Testbench Rambus MIPI Testbench from Rambus emulates a MIPI device enabling end-to-end simulation of a MIPI design. This includes the follow features: • Separ...

1311 0.0

PCIe Controller Testbench PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design. This includes the following features: • R...

1312 0.0

PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface Rambus PCIe 3.0 with AXI is a configurable and scalable PCIe controller Soft IP designed for ASIC and FPGA implementation. Rambus PCIe 3.0 with AXI is...

1313 0.0

PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support Rambus PCIe 3.0 Controller is a highly configurable PCIe 3.0 interface Soft IP designed for ASIC and FPGA implementations supporting endpoint, root po...

1314 0.0

ASIL-B Ready ISO 26262 Certified VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter The DisplayPort Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA Displa...

1315 195.0

PCIe 7.0 Retimer Controller The Rambus PCI Express® (PCIe®) 7.0 Retimer Controller provides a complete digital data path solution that delivers best-in-class latency, power and a...

1316 190.0

PCIe 6.2 Switch The Rambus PCI Express® (PCIe®) 6.2 Switch is a customizable, multiport embedded switch for PCIe designed for ASIC implementations. It enables the con...

1317 70.0

CXL 3.0 IP EMPOWER YOUR DESIGN WITH UNMATCHED CXL PERFORMANCE Highly advanced and versatile CXL Controller IP that empowers your design with unparalleled spee...

1318 3.0

Multi-Link Multi-Protocol SerDes 16Gbps in TSMC 28HPC Terminus Circuits offers low power, low latency Multistandard SerDes in TSMC 28nm process node to support wide range of standards like PCI Express, SA...

1319 0.0

AHB Channel with Decoder and Data Mux The AHB Channel provides the necessary infrastructure to connect as many as 7 AHB Slaves (numbered 1-7) to an AHB bus Master. The AHB Channel perform...

1320 23.0

DisplayPort Transmitter Link Controller Our 5th generation DisplayPort Transmitter Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link r...

1321 23.0

DisplayPort Receiver Link Controller Our 5th generation DisplayPort Receiver Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link rate...

1322 25.0

Flash SPI controller master/slave Veriest's SPI Master Controller IP provides an industry standard data communication channel between the AMBA APB and SPI buses. It supports SPI master...

1323 1.0

SMIC 0.18um PCI-X IO The PCI-X transceiver is a IP version of PCI-X I/O pads, which is fully compatible with PCI-X R1.0 specification....

1324 1.0

USB1.1 PHY The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed...

1325 1.0

USB 1.1 PHY The USB1.1 PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB1.1 core with RCV, VM and VP. It is desig...

1326 1.0

USB1.1 PHY The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed...

1327 1.0

USB1.1 PHY The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed...

1328 1.0

USB 1.1 PHY The USB11PHY is an IP version of USB transceiver. It receives data with DP and DM and transfers data to USB11 core with RCV, VM and VP. It is designed...

1329 1.0

GSMC 0.15um 1.2V/3.3V PCI I/O Cells VeriSilicon GSMC 0.15um 1.2V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) ...

1330 0.0

APB Channel with Decoder and Data Mux The APB Channel provides the necessary infrastructure to connect as many as 16 AHB Slaves (numbered 0-15) to an APB Bus Master. The APB Channel perfo...

1331 1.0

GSMC 0.18um PCI I/O Cells Library VeriSilicon GSMC 0.18um 1.8V/3.3V PCI I/O Cells Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC)...

1332 1.0

GSMC0.18um PCI I/O Cells DUP Library VeriSilicon GSMC 0.18um 1.8V/3.3V PCI I/O Cells Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC)...

1333 1.0

GSMC 0.25um 2.5V/3.3V PCI I/O Cell Library VeriSilicon GSMC 0.25um 2.5V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Grace Semiconductor Manufacturing Corporation (GSMC) ...

1334 1.0

SMIC 0.13um 1.2V/3.3V PCI I/O Cells Library VeriSilicon SMIC 0.13um 1.2V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation...

1335 1.0

SMIC 0.18um PCI I/O Cells Library VeriSilicon SMIC 0.18um 1.8V/3.3V PCI I/O Cells Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporatio...

1336 1.0

SMIC 0.18um PCI I/O Cells DUP Library VeriSilicon SMIC 0.18um 1.8V/3.3V PCI I/O Cells Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporatio...

1337 1.0

SMIC 0.25um 2.5V/3.3V PCI I/O Cells Library VeriSilicon SMIC 0.25um 2.5V/3.3V PCI I/O Cell Library developed by VeriSilicon is optimized for Semiconductor Manufacturing International Corporation...

1338 1.0

USB 1.1 PHY The USB1.1 PHY is an IP version of USB transceiver. It receives data with DP and DM, and transfers data to USB1.1 core with RCV, VM and VP. It is desi...

1339 1.0

SMIC 0.13um USB 1.1 PHY The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial Bus. It receives dat...

1340 1.0

IBM 65nm USB2.0 Dual Role PHY The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB anal...

1341 0.0

SPI Slave to AHB Lite Master The ISPI Slave to AHB Lite Master is commonly used as a monitor interface to allow external devices to access the internal AHB bus. A SPI Slave to ...

1342 1.0

SMIC 0.13um USB 1.1 PHY The USB1.1 PHY is an IP version of USB transceiver designed in standard logic to interface the physical layer of Universal Serial Bus. It receives dat...

1343 1.0

SMIC 65nm USB2.0 Dual Role PHY The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB anal...

1344 1.0

GSMC 0.18um USB 1.1 PHY The USB1.1 PHY is an IP version of USB transceiver. It receives data via DP and DM, and transfers data to USB1.1 core via RCV, VM and VP. It is design...

1345 1.0

TSMC 55nm USB2.0 Dual Role PHY The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB anal...

1346 1.0

HLMC 55nm EF MIPI DPHY V1.2 This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes. It can support both...

1347 1.0

GLOBALFOUNDRIES 22nm FDX MIPI DPHY Slave V1.2 This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes. It can support Slave side. Each l...

1348 1.0

GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V2.1/V3.0 This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of Bi-directional 1-Clock and 4-Data lanes. It c...

1349 1.0

SMIC 0.11um USB2.0 Dual Role PHY The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard. It provides a High/Full-Speed USB anal...

1350 1.0

GLOBALFOUNDARIES 22nm FDSOI USB3.0 Dual Role PHY/OTG PHY This USB3.0 PHY IP is designed according to USB3.0 and USB2.0 specification. It supports the USB3.0 5Gbps Super-Speed mode and is backward compatible ...