1351 3.0

MIPI RFFE Master IP SmartDV’s MIPI RFFE (Radio Frequency Front-End) Master IP is a silicon-proven solution designed for high-speed, low-latency control of RF front-end co...

1352 16.0

3.3V general purpose I/O for 28nm CMOS The 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.8V thick oxide MOS devices. It ...

1353 0.0

SPI to AXI Bridge The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...

1354 16.0

1.8V general purpose I/O for 4nm FinFET The Sofics 1.8V capable GPIO is an IP macro for on-chip integration. It is a 1.8V general purpose I/O built with a stack of 1.2V MOS FINFET devices. I...

1355 12.0

USB 2.0 Device Transceiver PHY ...

1356 16.0

USB2.0 Host Transceiver PHY USB 2.0 HOST Transceiver is a fully integrated PHY Core which is a super-set of HOST PHY with High Speed (HS), Full-Speed (FS) and Low-Speed Transceiv...

1357 12.0

PCI Express PHY serial link PIPE Transceiver IP cell/hard macro SMS5000 is a fully integrated CMOS transceiver that handles the full Physical Layer PCI Express protocol and signaling. It contains all necessary AFE ...

1358 12.0

Serial ATA (SATA) I/II PHY IP CORE SMS6000 is a Serial ATA gen I and gen II compliant PHY IP which supports SAPIS and Serial Attached SCCI (SAS) specifications both at 1.5 Gbp/s and 3.0...

1359 6.0

USB 2.0 PHY; SMIC 40nm LL ...

1360 6.0

MIPI Rx D-PHY ...

1361 6.0

USB 2.0 PHY; SMIC 55nm LL ...

1362 50.0

TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

1363 50.0

TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries, multiple metalstacks Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

1364 0.0

AHB Slave to SPI Master The AHB-Lite to SPI Bridge is used to translate 32-bit AHB-Lite Writes and Reads to Writes and Reads over a SPI interface. A custom 32-bit protocol i...

1365 20.0

TSMC 5nm (N5) 2.5V Basekit Libraries Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

1366 20.0

TSMC 5nm (N5) 1.2V/1.8V I3C Libraries Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

1367 20.0

TSMC 4nm (N4P) 1.2V/1.8V I3C Libraries Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

1368 20.0

IO I3C 3.3V in GF (22nm) Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

1369 50.0

TSMC 3nm (N3E) 1.2V/1.8V GPIO Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

1370 50.0

TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

1371 50.0

TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries, multiple metalstacks Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

1372 20.0

TSMC 6nm (6FF) 3.3V GPIO Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

1373 20.0

TSMC 7nm (7FF) 3.3V GPIO Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

1374 20.0

TSMC 5nm (N5) 1.2V/1.8V Failsafe GPIO Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

1375 0.0

AHB Performance Subsystem - ARM Cortex M0 The AHB Performance Subsystem is an AMBA® based system that is useful as the digital infrastructure for building low power SOCs needing additional per...

1376 20.0

TSMC 5nm (N5) 1.2V/1.8V Failsafe GPIO Libraries, multiple metalstacks Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

1377 20.0

TSMC 5nm (N5) 1.2V/1.8V/2.5V Failsafe GPIO Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

1378 20.0

TSMC 5nm (N5) 1.2V/1.8V/2.5V GPIO Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

1379 20.0

TSMC 5nm (N5) 1.2V/1.8V/2.5V GPIO Libraries, multiple metalstacks Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

1380 20.0

TSMC 4nm (N4P) 1.2V/1.8V/2.5V Failsafe GPIO Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

1381 20.0

IO 1.2V GPIO in Samsung (4nm) Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

1382 20.0

IO 1.8V GPIO in Samsung (4nm) Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

1383 0.0

AHB AES with DMA The Advanced Encryption Standard (AES) IP Core is a complete hardware implementation encryption/decryption algorithm described in the U.S. Government ...

1384 50.0

TSMC 3nm (N3E) 1.8V SD/eMMC PHY Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

1385 50.0

TSMC 3nm (N3E) 1.8V SD/eMMC IO Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

1386 50.0

TSMC 3nm (N3E) 1.8V SD/eMMC PHY, multiple metalstacks Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

1387 20.0

TSMC 5nm (N5) 1.8V SD/eMMC IO Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

1388 20.0

TSMC 5nm (N5) 1.8V SD/eMMC PHY Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

1389 20.0

TSMC 5nm (N5)1.8V SD/eMMC PHY, multiple metalstacks Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

1390 20.0

TSMC 4nm (N4P) 1.8V SD/eMMC IO Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

1391 20.0

TSMC 4nm (N4P) 1.8V SD/eMMC PHY Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

1392 20.0

IO 3.3V eMMC in GF (22nm) Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

1393 50.0

TSMC 3nm (N3E) 1.5V LVDS Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

1394 0.0

AHB-Lite to AHB-Lite Asynchronous Bridge The AHB-Lite to AHB-Lite Asynchronous Bridge translates an AHB-Lite bus transaction (read or write) on one clock domain to an AHB-Lite bus transacti...

1395 50.0

TSMC 3nm (N3E) 1.2V LVDS Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

1396 20.0

TSMC 7nm (7FF) 1.8V LVDS Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

1397 20.0

IO 1.8V LVDS in GF (22nm) Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

1398 20.0

IO 3.3V LVDS Rx in GF (12nm) Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

1399 20.0

IO 1.8V LVDS Rx in GF (12nm) Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

1400 20.0

TSMC 6nm (6FF) 3.3V SMBUS (I2C) IO Synopsys Inter-Integrated Circuit (I2C) I/O library is used for two wire interfaces to connect low-speed devices like EEPROM, A/D, and D/A converters ...