1551 7.5

USB 3.0 Device Controller (Exclusively for Turnkey ASIC design; not for standalone licensing) USB3.0 Device Controller IP Core provides an integrated and customizable solution for USB3.0 Device applications. The Core is compliant with USB3.0/2....

1552 7.5

USB 3.0 Retimer (Exclusively for Turnkey ASIC design; not for standalone licensing)" USB3.0 Retimer softcore is designed for use USB Port/Cable Retimer applications. The requirements set forth in the specification comprehend the use of...

1553 7.5

USB 2.0 Host controller (Exclusively for Turnkey ASIC design; not for standalone licensing) USB 2.0 Host Controller supports high (480 Mbps), full (12 Mbps) and low (1.5 Mbps) speed operation. Supports Control, Bulk, Isochronous and Interrupt...

1554 7.5

USB 2.0 Device controller (Exclusively for Turnkey ASIC design; not for standalone licensing) USB 2.0 Device controller implements a complete high/full speed peripheral controller that interfaces UTMI USB port transceiver on one side and to an ...

1555 0.0

I2C Slave Controller w/FIFO (APB Bus) The Digital Blocks DB-I2C-S-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0 APB...

1556 7.5

I2C Master/Slave Controller (Exclusively for Turnkey ASIC design; not for standalone licensing) I2C slave enables communication with an I2C master using the standard I2C protocol. It is designed for easy integration into SoC, such as sensors or m...

1557 7.5

SPI Master/Slave Controller (Exclusively for Turnkey ASIC design; not for standalone licensing) SPI Controller IP enables synchronous serial communication with slave or master peripherals. It has Generic interface which programs the control and d...

1558 7.5

UART/Serial Port (Exclusively for Turnkey ASIC design; not for standalone licensing) The Serial Port IP (RS232, RS422, RS485) is a Single Port Standalone IP, which supports all the features in the modes like 16C450, 16C550, 16C550Ex, 1...

1559 7.5

IEEE1284 Parallel Port Controller (Exclusively for Turnkey ASIC design; not for standalone licensing) The IEEE1284 compliant parallel port controller supports faster data rates up to 2.0Mbytes/sec. It supports Nibble mode, Byte Mode, EPP, and ECP. Auto...

1560 7.5

Generic GPIO Controller (Exclusively for Turnkey ASIC design; not for standalone licensing) General Purpose I/O pins are used for system control and connection of various devices. This (GPIO) controller provides dedicated general-purpose pins...

1561 0.0

Synopsys 224G Ethernet PHY IP for TSMC N3P The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...

1562 7.0

MIPI RX PHY in SMIC28nm MIPI RX PHY is a mass production IP for D-PHY v1.2 and C-PHY v1.2 protocols. It includes a total of 5 Lanes, among which there are 4 data lanes and 1...

1563 7.0

MIPI RX controller in SMIC28nm MIPI RX controller is a mass production IP in SMIC 28nm supported MIPI DSI & DCS protocols....

1564 20.0

USB 3.0 PHY in TSMC (65nm, 55nm, 40nm, 28nm) The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer a...

1565 0.0

I2C Slave Controller w/FIFO (AHB Bus) The Digital Blocks DB-I2C-S-AHB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC or other high performance microprocessor via the AMBA 2.0/3.0...

1566 7.0

DSC decoder IP DSC decoder IP is compliant with standard VESA Display Stream Compression version 1.1/1.2/1.2a....

1567 0.0

A standard‑compliant I2S‑to‑AHB bridge A standard‑compliant I2S‑to‑AHB bridge that seamlessly connects digital audio streams to system memory and processors while fully adhering to AMBA® 4 ...

1568 0.0

A standard‑compliant parallel‑to‑AHB bridge A standard‑compliant parallel‑to‑AHB bridge that efficiently transfers parallel data streams into the system bus while fully adhering to AMBA® 4 speci...

1569 8.5077

PCIe 4.0 PHY (4nm) The Qualitas' 4nm PCIe PHY IP consists of hardmacro PMA and softmacro PCS compliant to PCIe Base 4.0 specification. This IP offers a cost-effective an...

1570 6.5077

Multi-Standard SerDes PHY (4nm) The MSS PHY IP consists of a hard macro PMA architecture supporting multi-standard NRZ signaling up to 20 Gbps, compliant with PCIe Gen4, DisplayPort ...

1571 6.5077

USB Super Speed+ PHY (4nm) The USB PHY IP consists of a hard macro PMA and soft macro PCS compliant with USB 3.2 specification, supporting SuperSpeed+ (10 Gbps) operation. This ...

1572 5.5077

SLVS-EC 2.0 RX PHY (14nm) The SLVS-EC Receiver PHY IP consists of a hard macro architecture compliant with SLVS-EC version 2.0 specification, supporting data rate up to 10 Gbps...

1573 5.5077

SLVS-EC 3.0 RX PHY (4nm) The SLVS-EC Receiver PHY IP consists of a hard macro architecture compliant with SLVS-EC version 3.0 specification, supporting data rate up to 10 Gbps...

1574 5.5077

eDP v1.5a RXPHY (14nm) The eDP RX PHY supports a maximum data rate of up to HBR3 (8.1 Gbps), and the general mode supports a maximum data rate of up to 4 Gbps. This core IP ...

1575 5.5077

DP 2.1a / eDP v2.0 RXPHY (4nm) The DP/eDP RX PHY consists of hardmacro PHY compliant to DP v2.1a and eDP v2.0 specification, supporting maximum data rate of up to UHBR(20Gbps) opera...

1576 0.0

UDP/IP Hardware Protocol Stack - 100G The Digital Blocks DB-UDP-IP-100GbE-AMBA is a UDP/IP Hardware Stack / UDP Off-load Engine (UOE) with low latency, high-performance targeting 100 GbE n...

1577 0.0

32G SerDes PHY IP in 28nm The 32G SerDes IP enables ultra-fast serial communication at up to 32 Gbps per channel, providing a scalable and production-ready solution for high-pe...

1578 0.0

112G Serdes PHY IP in 5nm The 112 Gbps SerDes PHY IP Core, natively developed in 5 nm FinFET, unlocks unmatched serial speeds for SoC interconnects, supporting both PAM4 (56–11...

1579 0.0

112G SerDes IP Core in 6nm The 112G SerDes PHY IP Core in 6nm offers best-in-class serial link performance for advanced SoC designs. Supporting multi-rate operation from 1 Gbps ...

1580 0.0

112G SerDes PHY IP in 12nm The 112G SerDes PHY IP Core, fabricated in 12nm FinFET technology, delivers scalable high-speed connectivity for modern SoC platforms. Supporting up t...

1581 5.5077

DP 1.4 / eDP v1.4b TXPHY (14nm) The eDP v1.4b TX PHY IP consists of a hard macro architecture supporting embedded DisplayPort v1.4 specification with data rates up to 8.1 Gbps per la...

1582 5.5077

DP 2.1a / eDP v2.0 TXPHY (4nm) The DP/eDP TX PHY consists of hardmacro PHY compliant to DP v2.1a and eDP v2.0 specification, supporting maximum data rate of up to UHBR(20Gbps) opera...

1583 5.5077

DP 1.4 / eDP v1.4b TXPHY (8nm) The eDP v1.4b TX PHY IP consists of a hard macro architecture supporting embedded DisplayPort v1.4 specification with data rates up to 8.1 Gbps per la...

1584 9.5077

PCIe 6.0 PHY (8nm) The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe Base 6.x specification. This IP offers a cost-effective and low-power so...

1585 9.5077

PCIe 6.x and 56G Ethernet Combo PHY (8nm) The SERDES PHY includes the functions of both PCIe PHY and Ehternet PHY. The PCIe PHY IP consists of hardmacro PMA and softmacro PMD compliant to PCIe...

1586 15.0

3.3V general purpose I/O for 4nm FinFET The Sofics 3.3V capable GPIO is an IP macro for on-chip integration. It is a 3.3V general purpose I/O built with a stack of 1.2V (1.5V overdrive) MOS ...

1587 0.0

I2C/SMBus Master/Slave Controller w/FIFO (AXI/AHB/APB) The Digital Blocks DB-I2C-SMBus-MS-AMBA Controller IP Core is an I2C/SMBus Master/Slave Controller, interfacing a microprocessor via the AMBA AXI, AHB...

1588 0.0

ASA-ML Serdes IP Core in 28nm The ASA PHY IP Core in 28nm provides scalable and robust SerDes connectivity for advanced automotive SoCs. Supporting the Automotive SerDes Alliance s...

1589 0.0

ASA-ML Serdes IP Core in 22nm The ASA PHY IP Core in 22nm delivers next-generation automotive SerDes connectivity, enabling high-bandwidth, low-latency serial links for advanced au...

1590 0.0

AHB Lite to AXI Bridge The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and the...

1591 0.0

APB to AHB-Lite Asynchronous Bridge The APB to AHB-Lite Asynchronous Bridge translates an APB bus transaction (read or write) on one clock domain to an AHB-Lite bus transaction on a seco...

1592 0.0

APB I2C Master/Slave Controller The I2C Interface provides full support for the two-wire I2C synchronous serial interface, compatible with the ACCESS Bus physical layer, with additio...

1593 0.0

eUSB2 PHY on Samsung SF4X The Embedded USB 2.0 PHY is a High speed System-on-Chip (SoC) integrated transceiver IP in advanced process that implements the Intel® UTMI standard. ...

1594 0.0

USB3.2 PHY on Samsung SF4X This IP is a USB 3.2 Gen2x2 PHY IP which provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 20Gbps. The USB 3.2 Gen2x2 I...

1595 0.0

I3C Master / Slave Controller w/FIFO (APB Bus) The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – Improv...

1596 0.0

USB3.2 PHY on Samsung S8LPU This IP is a USB 3.2 Gen2x2 PHY IP which provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 20Gbps. The USB 3.2 Gen2x2 I...

1597 0.0

MIPI CDPHY TX & RX V2.1/V3.0 This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of Bi-directional 1-Clock and 4-Data lanes. It c...

1598 0.0

MIPI CDPHY TX & RX V2.1/V3.0 This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of Bi-directional 1-Clock and 4-Data lanes. It c...

1599 12.0

JESD204b Deser PHY GF 22FDX/ GF 22FDX-PLUS InCirT offers Deserializer PHY that is implemented in Global Foundries 22FDX CMOS technology. The IP macro offers 2x lanes with data rates from 6.375 ...

1600 12.0

JESD204b Ser PHY GF 22FDX/ GF 22FDX-PLUS InCirT offers Serializer PHY that is implemented in Global Foundries 22FDX CMOS technology. The IP macro offers 1x lane with data rates from 6.375 Gbp...