1901 3.0

AHB2APB Bridge IP Truechip's AHB2APB Bridge IP provides chip designers and architects, an efficient way to connect Different Bus Protocol based IPs with reduced latency...

1902 0.0

AHB / AXI4 - Lite to AXI4-Stream Bridge The MM2ST IP core bridges the streaming interfaces of a peripheral or accelerator to a memory-mapped AMBA® AHB or AXI4-Lite bus. Designed for ease ...

1903 0.0

SPI to AHB - Lite Bridge The SPI2AHB core implements an SPI slave to AHB-Lite master bridge. It allows an external SPI master to perform read or write access to any memory-map...

1904 0.0

DP1.2 Transmitter PHY Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...

1905 0.0

I3C INNOSILICON™ I3C IP is fully compatible with the MIPI I3C and JESD403-1B standard and backward compatible to I2C. It enhances the existing I2C IP by n...

1906 0.0

UFS Device IP The SmartDV UFS DEVICE IP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The UFS...

1907 0.0

112G-LR PAM4 SerDes PHY for Intel 112G-LR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps...

1908 0.0

112G-LR PAM4 SerDes PHY for Samsung 112G-LR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps...

1909 0.0

112G-LR PAM4 SerDes PHY for TSMC 112G-LR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbps...

1910 50.0

112G-VSR for TSMC 112G-VSR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbp...

1911 0.0

16G Multi-Protocol SerDes (MPS) PHY For TSMC Silicon-proven PHY for PCIe, USB, Ethernet, DisplayPort, and other protocols The 16 Gbps Multi-Protocol SerDes (MPS) PHYs are a high-performance se...

1912 100.0

224G-LR SerDes PHY for TSMC 224G-LR SerDes PHY enables 1.6T and 800G networks The ever-increasing bandwidth in high-performance computing (HPC) applications is driving the rap...

1913 200.0

224G-LR SerDes PHY for UALink for TSMC 224G-LR SerDes PHY enables 1.6T and 800G networks for UALink UALink, the standard for AI accelerator interconnects, facilitates this scalability by...

1914 0.0

56G-LR Pam4 SerDes for TSMC 56G LR SerDes PHY provides exceptional performance w/ best-in-class power & area, making it ideal for machine learning and 5G. The Cadence 56Gbps L...

1915 0.0

eUSB2v2 Controller Proven solution featuring host and peripheral eUSB2V2 scales up to 4.8Gbps of data rate with the flexibility to configure asymmetrical or symmetric...

1916 150.0

eUSB2V2 PHY for TSMC Low voltage USB 2.0 supporting 4.8Gbps eUSB2V2 is primarily a performance enhancement to eUSB2 native mode to provide more bandwidth for peripheral...

1917 0.0

PCIe 1.1 SerDes PHY for GLOBALFOUNDRIES Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The PCI...

1918 0.0

PCIe 1.1 SerDes PHY for Samsung Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The PCI...

1919 0.0

PCIe 1.1 SerDes PHY for TSMC Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The PCI...

1920 0.0

PCIe 2.1 SerDes PHY for GLOBALFOUNDRIES Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The PCI...

1921 0.0

PCIe 2.1 SerDes PHY for Samsung Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The PCI...

1922 0.0

PCIe 2.1 SerDes PHY for TSMC Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The PCI...

1923 0.0

PCIe 3.1 for GLOBALFOUNDRIES Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The 8Gb...

1924 0.0

PCIe 3.1 for Intel Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The 8Gb...

1925 0.0

PCIe 3.1 for Samsung Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The 8Gb...

1926 15.0

PCIe 3.1 for TSMC Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The 8Gb...

1927 0.0

PCIe 4.0 SerDes PHY for GLOBALFOUNDRIES Low-power, long-reach, multi-protocol PHY for PCIe 4.0 The Cadence 16G Multi-Link and Multi-Protocol PHY is a silicon-proven, high-end SerDes opera...

1928 0.0

PCIe 4.0 SerDes PHY for Samsung Low-power, long-reach, multi-protocol PHY for PCIe 4.2 The Cadence 16G Multi-Link and Multi-Protocol PHY is a silicon-proven, high-end SerDes opera...

1929 0.0

PCIe 4.0 SerDes PHY for TSMC Low-power, long-reach, multi-protocol PHY for PCIe 4.1 The Cadence 16G Multi-Link and Multi-Protocol PHY is a silicon-proven, high-end SerDes opera...

1930 50.0

PHY for PCIe 5.0 and CXL for Samsung Cadence 32G NRZ multi-;protocol PHY The Cadence 32G Multi-Protocol PHY IP for Samsung is a high--performance SerDes operating from 1.25Gbps to 32Gb...

1931 25.0

PHY for PCIe 6.0 and CXL for Intel 18A Most advanced PHY and Controller for HPC, AI, ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®)...

1932 0.0

USB Type-C and Power deliver Controller USB Type-C and Power deliver Controller...

1933 15.0

PHY for PCIe 6.0 and CXL for Samsung Automotive Most advanced PHY and Controller for HPC, AI, ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®)...

1934 75.0

PHY for PCIe 6.0 and CXL for TSMC Most advanced PHY and Controller for HPC, AI, ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®)...

1935 0.0

USB 2.0 PHY for Samsung Proven PHY IP for USB Device, Host, and OTG with small footprint and low active power The ubiquity of USB 2.0 in devices makes it nearly mandatory ...

1936 0.0

USB 3.x PHY for Intel Proven PHY IP for USB Device, Host, and DRD with small footprint and low active power The ubiquity of USB 3.x in devices makes it nearly mandatory ...

1937 0.0

USB 3.x PHY for Samsung Proven PHY IP for USB Device, Host, and DRD with small footprint and low active power The ubiquity of USB 3.x in devices makes it nearly mandatory ...

1938 4.5077

HSSTP PHY TX (5nm) (1.5 Gbps, 3 Gbps, and 6 Gbps) The HSSTP TX PHY is a 5nm hard macro supporting up to 6Gbps data rates with dual lanes and a hybrid mode driver for AC-coupled links. It includes feat...

1939 4.5077

HSSTP Link The High-Speed Serial Trace Port (HSSTP) Controller IP implements the ARM HSSTP protocol. HSSTP replaces the existing parallel data output port, enab...

1940 20.0

64G SerDes Multi-Gigabit/s serial transceivers are fast replacing older parallel interfaces in most of applications. The accelerating demand for higher data rate...

1941 1.0

SPI Master Serial Interface Controller Master serial interface compatible with the popular SPI standard. Features a simple command interface and permits multiple SPI slaves to be contro...

1942 1.0

SPI Slave Serial Interface Controller Slave serial interface compatible with the popular SPI standard. Permits an SPI Master to communicate with your FPGA, CPLD or ASIC device. The con...

1943 2.0

56G SerDes Ethernet 56G SerDes IP core supports PAM4 signaling in the range of 25.0-60.0 Gbps using full-rate and half-rate modes with scrambled data. Non-return-to-zero ...

1944 5.5077

112Gb/s PAM4 SERDES PHY (14nm) The Ethernet PHY IP is used for CEI-112G applications and serializes 8b/10b encoded data for Gen1 and Gen2, as well as 128b/130b encoded data for Gen3...