Design & Reuse
1928 IP
1901
20.0
CXL memory expansion
DenseMem increases effective CXL Type 3 Device memory capacity by a factor of 2x through transparent, in-line memory compression/decompression with mi...
1902
0.0
MIPI C-PHY 2.1 TX/RX, 6nm
InPsytech proudly presents our groundbreaking innovation, the MIPI C-PHY Ver2.1 IP, setting new standards in connectivity solutions. Designed to empow...
1903
0.0
MIPI C/D COMBO RX HS PHY UMC 28/22nm
Our silicon-proven MIPI C- and D-PHY combo Rx PHY is compliant with Camera Serial Interface (CSI) version 1.2, supporting D-PHY speeds up to 4.5 GHz (...
1904
0.0
MIPI C/D COMBO TX HS PHY UMC 28/22nm
The MIPI C/D combo PHY Tx IP is compliant with the Display Serial Interface (DSI) with D-PHY signaling up to 4.5GHz and C-PHY operating at a symbol ra...
1905
0.0
MIPI C/D COMBO TX PHY, 5nm
The MIPI C/D combo PHY Tx IP is compliant with the Display Serial Interface (DSI) with D-PHY signaling up to 4.5GHz and C-PHY operating at a symbol ra...
1906
0.0
MIPI D-PHY 1.2 TX/RX, 22nm
The MIPI D-PHY Tx IP is compliant with the Display Serial Interface (DSI) with D-PHY signaling up to 2.5GHz. This IP is designed for extreme low power...
1907
0.0
MIPI D-PHY Tx 2.5G and MIPI D-PHY Rx 2.5G (Automotive Interface IP)
InPsytech Inc., an Automotive interface IP solution provider, introduces its latest Automotive High-Speed Interface IP Series, designed to meet the ri...
1908
0.0
MIPI DPHY TX PHY, UMC 22nm ULP/ULL
The MIPI D-PHY Tx IP is compliant with the Display Serial Interface (DSI) with D-PHY signaling up to 2.5GHz. This IP is designed for extreme low power...
1909
0.0
UMC MIPI D-PHY Tx 2.5G and MIPI D-PHY Rx 2.5G (Automotive Interface IP)
Egis Technology Inc., an Automotive interface IP solution provider, introduces its latest Automotive High-Speed Interface IP Series, designed to meet ...
1910
20.0
DSC Decoder
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data compression and has b...
1911
20.0
DSC Encoder
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data compression and has b...
1912
0.0
HDMI module cecTalker
The HDMI module cecTalker(pronounced "C-E-C-Talker") enables the user to easily design UI and UX for devices in order to make them convenien...
1913
0.0
DisplayPort 1.4a IP Core
DisplayPort heralds a new alternative in video connectivity. Designed to enable low cost direct drive monitors and backed by industry leaders (Intel, ...
1914
0.0
HDMI(Ver2.1) Receiver IP for TSMC 28nm Process
The SLIFHDMIR21TM28 provides a complete single-link HDMI receiver function complies with HDMI specification version 2.1. The SLIFHDMIR21TM28 consists...
1915
0.0
HDMI Ver.2.1 Transmitter IP for TSMC 28nm HPC+
The SLIFHDMIT21TM28 provides a complete single-link HDMI transmitter function complies with HDMI specification version 2.1. The SLIFHDMIT21TM28 consis...
1916
0.0
DisplayPort 1.4 Transmitter Link Controller
Continuing the highly successful line of DisplayPort link controller cores, the Trilinear VF-111T DisplayPort Transmitter core has been updated to inc...
1917
3.0
AHB2APB Bridge IP
Truechip's AHB2APB Bridge IP provides chip designers and architects, an efficient way to connect Different Bus Protocol based IPs with reduced latency...
1918
0.0
AHB/AXI4-Lite to AXI4-Stream Bridge
The MM2ST IP core bridges the streaming interfaces of a peripheral or accelerator to a memory-mapped AMBA® AHB or AXI4-Lite bus. Designed for ease ...
1919
0.0
SPI to AHB-Lite Bridge
The SPI2AHB core implements an SPI slave to AHB-Lite master bridge. It allows an external SPI master to perform read or write access to any memory-map...
1920
0.0
DP1.2 Transmitter PHY
Innosilicon DP TX IP is designed to transmit video, audio and auxiliary data from system host device to a display device for display applications. In...
1921
0.0
I3C
INNOSILICON™ I3C IP is fully compatible with the MIPI I3C and JESD403-1B standard and backward compatible to I2C. It enhances the existing I2C IP by n...
1922
0.0
UFS Device IP
The SmartDV UFS DEVICE IP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SoC or FPGA development. The UFS...
1923
0.0
USB Type-C and Power deliver Controller
USB Type-C and Power deliver Controller...
1924
0.0
HSSTP PHY TX (5nm) (1.5 Gbps, 3 Gbps, and 6 Gbps)
The HSSTP TX PHY is a 5nm hard macro supporting up to 6Gbps data rates with dual lanes and a hybrid mode driver for AC-coupled links. It includes feat...
1925
0.0
HSSTP Link
The High-Speed Serial Trace Port (HSSTP) Controller IP implements the ARM HSSTP protocol. HSSTP replaces the existing parallel data output port, enab...
1926
20.0
64G SerDes
The KNiulink 64G SerDes IP core supports PAM4 signaling in the range of 25.0 - 64.0 Gbps using full-rate and half-rate modes with scrambled data. Non-...
1927
2.0
56G SerDes Ethernet
56G SerDes IP core supports PAM4 signaling in the range of 25.0-60.0 Gbps using full-rate and half-rate modes with scrambled data. Non-return-to-zero ...
1928
1.0
112Gb/s PAM4 SERDES PHY (14nm)
The Ethernet PHY IP is used for CEI-112G applications and serializes 8b/10b encoded data for Gen1 and Gen2, as well as 128b/130b encoded data for Gen3...