51 3.0

Generic Polar FEC Codec Creonic has flexible Polar decoder architecture to fulfil different customer requirements. The IP core has been demonstrated on internal conferenc...

52 1.0

5G-NR LDPC Decoder 5G NR is the mobile broadband standard of the 5th generation. A new rate compatible structure for LDPC codes are employed for channel coding to fulfil...

53 1.0

CCSDS SCCC Turbo Encoder and Decoder The recommended CCSDS 131.2-B-1 standard introduces a Serial Concatenated Convolutional Code (SCCC). Main goal of this code is to allow an efficient u...

54 3.0

Fixed-Point AWGN Channel The Creonic AWGN Channel IP is a noise generator capable of processing up to a maximum of 512 symbols in parallel. The IP was developed with the aim o...

55 1.0

CCSDS 231.0 LDPC Encoder and Decoder The CCSDS 231.0 LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rate 1/2, coded block lengths 128 and 5...

56 20.0

64G SerDes The KNiulink 64G SerDes IP core supports PAM4 signaling in the range of 25.0 - 64.0 Gbps using full-rate and half-rate modes with scrambled data. Non-...

57 2.0

DVB-GSE Encapsulator and Decapsulator The DVB-GSE encapsulator and decapsulator IP cores close the gap between network protocols like Ethernet and the physical layer of the DVB family of s...

58 1.0

DVB-RCS2 Multi-Carrier Receiver DVB-RCS2 (Digital Video Broadcast – Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digit...

59 16.0

8b/10 Decoder The 8b10b line code is widely used to achieve DC-balance and bounded disparity when transmitting serial data over a medium. It ensures enough state tr...

60 25.0

Ethernet 10/100 PHY The KA13ETHB33 is a single-port PHY with an MII (Media Independent Interface). It implements all 10/100M Ethernet Physical- layer functions including ...

61 1.0

XAUI PHY The Innosilicon XAUI PHY is a highly programmable module that processes high-speed serial data to parallel data compatible with the IEEE802.3 standard...

62 0.0

GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SAM 14LPP The GPHY is a fully integrated IP Core with low power consumption for Giga 10/100/1000 Ethernet applications. It can operate in 10BASE-T, 100BASE-TX, ...

63 5.0

Synchronous Ethernet (SyncE) ESMC and Enhanced ESMC core NetTimeLogic’s Synchronous Ethernet (SyncE) Node is a full hardware (FPGA) only implementation of an ESMC frame Handler and State selector. The whole ...

64 2.0

Binary-FSK Demodulator 16-bit BFSK demodulator with complex or real data samples. Suitable for passband or baseband operation. Ideal for use in low cost / low power RF appl...

65 2.0

Binary-PSK Demodulator 16-bit BPSK demodulator ideal for low-cost radio links over a few 100m. Features automatic carrier lock with no complex PLL setup or tuning required. ...

66 1.0

SPI Master Serial Interface Controller Master serial interface compatible with the popular SPI standard. Features a simple command interface and permits multiple SPI slaves to be controll...

67 38.0

100G Ethernet MAC/RS The Alphawave CGMAC-PCS-Lite IP core consists of the CGMAC core and the CGPCS-Lite core. It is an excellent solution to the 100G Ethernet over OTN app...

68 1.0

SPI Slave Serial Interface Controller Slave serial interface compatible with the popular SPI standard. Permits an SPI Master to communicate with your FPGA, CPLD or ASIC device. The contr...

69 1.0

Packet-based Digital Radio Link Fully custom Digital Radio Link based on either our FSK or PSK modulation schemes. Data is split into packets or frames and modulated for transmissio...

70 6.0

10/100 Ethernet PHY, TSMC 28nm HPC+ -10 100ETHERNET-T28HPCP18 is a single-port DSP-based Fast Ethernet Transceiver. It contains all the ac?tive circuitry required to convert data stream ...

71 6.0

Single port 10/100 Fast Ethernet Transceiver - TSMC12nm FFC SP-10 100ETHERNET-T12FFC is a single-port DSP-based Fast Ethernet Transceiver. It contains all the active circuitry required to convert data stream t...

72 6.0

10/100 Ethernet PHY for TSMC 22nm ULP 10 100ETHERNET-T22ULP18 is a single-port DSP-based Fast Ethernet Transceiver. It contains all the ac?tive circuitry required to convert data stream to...

73 80.0

LDPC Encoder/Decoder (LDPC) Mobiveil’s LDPC Encoder / Decoder* is a flash reliability solution delivering industry-leading flash endurance and retention through advanced LDPC err...

74 0.0

D-MAC-10/100 Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external ...

75 0.0

Used for controlling HDLC/SDLC transmission protocols The DHDLC IP Core provides versatile support for a widely used HDLC transmission protocol. It manages the bit stuffing process, both address appending...

76 0.0

Serial Peripheral Interface – Master/Slave with Octal, Quad, Dual and Single SPI Bus support The SPI IP is a revolutionary octal SPI designed to offer the fastest operations available for any serial SPI memory. It is flexible enough to interfa...

77 38.0

100G Ethernet PCS/FEC The Alphawave CGPCS IP core is an innovative implementation of the 802.3ba 100G PCS with an optional 802.3bj forward error correction (FEC) layer. It ...

78 0.0

QSPI FLASH Controller – XIP functionality (SINGLE, DUAL and QUAD SPI Bus Controller with Double Data Rate support) The SPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and phase of serial cloc...

79 0.0

GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in UMC 28HPC The GPHY is a fully integrated single chip for Gigabit Ethernet applications with lowest power consumption. It is capable of functioning in 10BASE-T, ...

80 0.0

Gigabit Ethernet 802.3 MAC Controller IP The Giga MAC IP is an embedded Fast Ethernet controller module. It is compliant with IEEE 802.3 specification for 10/100Mbps Ethernet and the IEEE802....

81 0.0

DVB-S2X WideBand Demodulator & Decoder IP (Silicon Proven) This is a high-performance, dual high-symbol-rate (HSR) DVB-S2/S2X demodulator IP extarcted from production chipsets with integrated tuner and silcon ...

82 0.0

DVB-S2X WideBand Demodulator IP This is a high-performance, dual high-symbol-rate (HSR) DVB-S2/S2X demodulator IP extarcted from production chipsets with integrated tuner and silcon ...

83 0.0

DVB-S2X LDPC/BCH Decoder IP (Silicon Proven) The DVB-S2/S LDPC/BCH decoder a silicon proven IP extracted from production chips has an octal input interface and a single output interface. The data...

84 0.0

DVB-S2X NarrowBand Demodulator IP This is NarrowBand demodulator IP is silicon proven and extratced from production chipsets, it performs demodulation according to DVB-S, legacy Direct...

85 0.0

Networking SerDes IP, Silicon Proven in ST 28FDSOI The 28 Gbps SerDes PHYs are comprehensive IP solutions that deliver enterprise-class performance across the challenging signaling environments typical...

86 0.0

ISDB-S3-LDPC-BCH Decoder IP This design is a ISDB-S3-LDPC-BCH Decoder IP, ready to license, verified and packaged, and supplied as a portable and synthesizable Verilog IP. The sy...

87 0.0

BCH Decoder IP The BCH decoder has four main functional blocks along with memory blocks. Syndrome calculation block calculates syndrome components which tell about p...

88 38.0

10G/25GBASE-R MAC Core The fully integrated Physical Coding Sublayer (PCS), KR4 FEC and Media Access Controller (MAC) core for 25Gbps Ethernet applications are compliant wit...

89 0.0

LDPC Decoder IS-GPS-800D IP The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parity Check (LDPC) Forwar...

90 0.0

DVB-T2/Lite LDPC Decoder IP In Digital video broadcasting for terrestrial broadcasting systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Chec...

91 20.0

DVB-S2 LDPC Decoder IP In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Dens...

92 0.0

DVB-S2X-LDPC Decoder IP In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Dens...

93 0.0

DVB-S2-LDPC-BCH IP The DVB-S2-LDPC-BCH block is a powerful FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite. In Digital video broad...

94 0.0

DVB-T2-LDPC-BCH IP In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC (Forward Error Correction) sub-system is needed. FEC...

95 0.0

DVB-C2 LDPC Decoder IP The Digital video broadcasting for cable systems systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes c...

96 0.0

Viterbi Decoder Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors....

97 0.0

GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 28HPC Ethernet PHY is an IEEE 802.3u compliant single-port Ethernet physical layer transceiver, and low power consumption transceiver for 10BASE-Te, 100BASE...

98 0.0

GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 40LP An IEEE 802.3u compliant single-port Ethernet physical layer transceiver with low power consumption for 10BASE-Te and 100BASE-TX operation is known as...

99 38.0

10G/25GBASE-R PCS+KR4 FEC IP Core The fully integrated Physical Coding Sublayer (PCS), KR4 FEC and Media Access Controller (MAC) core for 25Gbps Ethernet applications are compliant wit...

100 60.0

Silicon Proven 1G Ethernet PHY IP as Whitebox 1G Ethernet PHY IP Core is available for licensing as a Whitebox IP, with unlimited usage and full modification rights granted to the customer, ensuri...