101 0.0

Flash Memory LDPC LDPC corrects errors caused by flash storage failure mechanisms. The data is encoded while writing into the storage devices and it is decoded while re...

102 0.0

CCSDS AR4JA LDPC Encoder/Decoder AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3, and 3/4). To obtain h...

103 4.0

LDPC Decoder for IS-GPS-800D Applications The IS-GPS-800D standard defines an irregular Parity Check Matrix (PCM) for 2 subframes (2 and 3) encoded using Low Density Parity Check (LDPC) Forwar...

104 6.0

LDPC Decoder for DVB-S2 In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Dens...

105 2.0

LDPC Decoder for DVB-C2 In Digital video broadcasting for cable systems systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes c...

106 2.0

LTE Turbo decoder This block is suitable for 3GPP Long Term Evolution (LTE) applications compatible with the 3GPP Technical Specification. The LTE Release-8 Turbo code ...

107 1.0

HomePlug Turbo Decoder On the transmitter side, the PHY layer receives its inputs from the Media Access Control (MAC) layer. There are three separate processing chains: A) H...

108 4.0

Non-binary LDPC Decoder A powerful Forward Error Correction (FEC) subsystem is needed in almost all wireless communication systems. Low-Density Parity-Check (LDPC) codes are ...

109 6.0

AR4JA LDPC Decoder AR4JA LDPC decoder is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3 and 3/4). To obtain hi...

110 8.0

LDPC Decoder for 802.11 This is an LDPC decoder compliant with the IEEE 802.11 n/ac/ax standards. It supports high throughput,...

111 0.118

10/100 Ethernet PHY IP, UMC 90nm SP process 10/100 Base-TX Fast Ethernet PHY, UMC 90nm SP/RVT Low-K Logic process....

112 0.118

10/100 Ethernet PHY IP, UMC 0.13um HS/FSG process 10/100 Base-TX Fast Ethernet PHY, UMC 0.13um HS/FSG Logic process....

113 0.118

10/100 Ethernet PHY IP, UMC 0.18um MS process 10/100 Base-TX Fast Ethernet PHY, UMC 0.18um MMC process....

114 0.118

10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process 10BASE-T/100BASE-TX/100BASE-FX Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process...

115 0.118

0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature. 0.13um DSP Based Fast Ethernet PHY, based on FXEDP110HC0A HJ026a and add 100BASE-FX feature....

116 0.118

10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process 10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC/Low-K process...

117 0.118

10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC+/LOW_K process 10BASE-T/100BASE-TX/100BASE-FX/1000BASE-T Gigabit Energy Efficient Ethernet PHY; UMC 28nm HPC+/LOW_K process...

118 0.118

Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process. Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process....

119 0.118

10/100/1000 ETHERNET CONTROLLER_x005F_x005F_x005F_x005F_x005F_x000D_ WITH AHB AND AXI BUS_x005F_x005F_x005F_x005F_x005F_x000D_ 10/100/1000 ETHERNET CONTROLLER WITH AHB AND AXI BUS...

120 5.0

Ethernet TSN MAC 10G/25G Comcores TSN MAC 10G/25G provides a complete IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features including 802.1Qbu Preemption and ...

121 5.0

Ethernet Switch 1G/10G Comcores Ethernet Switch 1G/10G IP core is a highly configurable and size optimized implementation of a non-blocking crossbar switch that allows conti...

122 5.0

Ethernet MAC 10M/100M/1G/2.5G Comcores Ethernet MAC 10M/100M/1G/2.5G IP solution enables the host to communicate data using the IEEE 802.3 standard for the respective speeds and is...

123 5.0

Ethernet Switch 10G Comcores Ethernet Switch 10G IP core is a highly configurable and size optimized implementation of a non-blocking switch that allows continuous transm...

124 5.0

Ethernet TSN MAC 10M/100M/1G/2.5G Comcores TSN MAC 10M/100M/1G/2.5G provides a complete IEEE 802.3 Ethernet Layer 2 solution with support for key TSN features including 802.1Qbu Preemp...

125 7.0

Ethernet Switch 10G/25G Comcores compact high speed Ethernet switch offers state of the art performance offering four 25 Gbps ports and twelve 10 Gbps ports. The switch supp...

126 5.0

Ethernet MAC 10G/25G Comcores Ethernet MAC 10G/25G IP solution enables the host to communicate data using the IEEE 802.3 standard for the respective speeds and is suited f...

127 5.0

Ethernet TSN Advanced Switch 10M/100M/1G/10G/25G for 5G/ORAN and other applications Comcores Manticore 10M/100M/1G/10G/25G IP is an advanced Ethernet Switch with an extensive set of QoS features and statistics. The switch supports up ...

128 5.0

Ethernet MAC & PCS 10G/25G Comcores Ethernet MAC and PCS 10G/25G is a silicon agnostic implementation of the IEEE 802.3 standard. The Ethernet MAC IP includes the Reconsiliation...

129 5.0

Ethernet MAC 40G/100G Comcores Ethernet MAC 40G/100G IP solution enables the host to communicate data using the IEEE 802.3 standard for the respective speeds and is suited ...

130 0.0

Viterbi Decoder Viterbi decoders are commonly used to decode convolutional codes in communications systems. This Viterbi Decoder is a fully parallel implementation wh...

131 0.0

Reed-Solomon Decoder Reed-Solomon (RS) decoder is ideal for correcting errors that occur in clusters. Clustered bit errors are usual when there is frequency selective fadi...

132 3.0

NCR Processor NCR (Network Clock Reference) is a procedure to provide the master clock (i.e. time information) of the satellite to all its user terminals. Typically...

133 0.0

10/25/40/100G Ethernet MAC The Chevin Technology Ethernet MAC IP core can simplify the FPGA integration of Ultra low-latency 10/25/40/100G MAC Ethernet connectivity in Intel and...

134 10.0

40G / 50G UDP/IP Hardware Protocol Stack UDP UDPIP Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...

135 0.0

TCP/IP - 10/25/40/100G Ethernet TCP Offload Engine Chevin Technology’s TCP/IP Offload Engine is an FPGA Synthesisable Ethernet TCP/IP server/client in a lean and fast, all-RTL solution. Chevin Technolo...

136 0.0

10Gbit/s Ethernet UDT Server for FPGAs FPGA Synthesisable 10Gbit/s Ethernet UDT4 server for reliable long distance/high bandwidth data transfer...

137 0.0

ARP/ICMP Protocol for Ethernet The CT1006-XGARP/ICMP block adds RTL-hardened functions for ICMP and ARP to any FPGA application. The all-RTL block includes part of the ARP protoc...

138 0.0

UDP/IP - 10/25/40/100G Ethernet UDP/IP Offload Engine Chevin Technology’s 10/25/40/100G UDP/IP Offload Engine for FPGAs has low latency and bandwidth overhead, as it sends packets of data without confirm...

139 0.0

10/25/40/100G Ethernet PCS/PMA The Chevin Technology PCS/ PMA is an IP core that simplifies the FPGA integration of Ultra low-latency 10/25/40/100G Ethernet connectivity in Intel an...

140 0.0

10/25/40/100G MAC/PCS Ethernet IP Core The 10/25/40/100G MAC IP core is a Low-Latency Ethernet MAC with a latency of 44.8ns in 2749 LUTs for 10Gbit/s and 20.5ns in 2680 LUTs for 25Gbit/s. W...

141 0.0

25Gbit/s Ethernet MAC The Chevin Technology 25GMAC IP core provides Ultra Low-Latency 25Gbit/s Ethernet connectivity in Xilinx Virtex® UltraScale™ FPGAs. The 25GMAC can...

142 0.0

25Gbit/s Ethernet PCS The Chevin Technology 25GPCS provides Ultra low-latency 25Gbit/s Ethernet connectivity in Xilinx Virtex® UltraScale™ FPGAs. Ultra-low latency is achie...

143 0.0

25G LL MAC /PCS Ethernet IP for FPGA The Chevin Technology 25G LL MAC/PCS combines the 25G MAC and 25G PCS IP cores to obtain the lowest possible latency while simplifying the integration...

144 30.0

Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC) CoMira’s multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC) is fully configurable and pro...

145 8.0

Reed Solomon Decoder CYB-RS-de core implements the Reed Solomon decoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum nu...

146 8.0

Reed Solomon Encoder CYB-RS-en core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum nu...

147 6.0

OTN Processor The Gemini TPS5101MP OTN processors IP cores are a member of Tera-Pass’ product family for access applications. Gemini TPS5101MP processors support th...

148 6.0

OTN Processor The Gemini TPS5201MP OTN processors IP cores are a member of Tera-Pass’ product family for access applications. Gemini TPS5201MP processors support th...

149 6.0

40G OTN Processor, Muxponder The Apodis IPL4002M OTN processors ASICs are a member of Tera-Pass’ product family for access applications. Apodis IPL4002M processors support the fun...

150 6.0

20G OTN Processor, Muxponder The Apodis IPL4102M OTN processors ASICs are a member of Tera-Pass’ product family for access applications. Apodis IPL4102M processors support the fun...