201 5.0

SPI Serial Peripheral Interface Master/Slave The CC-SPI-AXI is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller. The SPI core can be efficiently implemen...

202 15.0

DVB-S2X Multi-Carrier Demodulator The Creonic DVB-S2X high performance multi-carrier demodulator performs all tasks of an inner receiver while processing up to 36 carriers in parallel....

203 0.0

GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in TSMC 28HPC+ For Gigabit 10/100/1000 Ethernet applications, the GPHY is a highly integrated single chip. It is a singleport, IEEE 802.3u/ab compatible, power effic...

204 0.0

GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SMIC 28SF The GPHY is a highly integrated single chip for Giga 10/100/1000 Ethernet applications with minimal power consumption. It is capable of operating in 1...

205 0.0

Express Serial Peripheral Interface IP Core eSPI controller is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of standard eSPI specification. Through its eSP...

206 0.0

FSPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support) The FSPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and phase of serial clo...

207 0.0

Octal SPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support) and DMA Support Octal SPI master is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of Macronix (MX66LM1G45G) Octal SPI REV.1.0 sp...

208 4.0

Home Plug Green PHY MAC Layer TX/RX ntHPGP_MAC IP core implements “Connectionless CSMA-Only Level-0 CCo“ MAC Layer functionality with Passive Coordination, as detailed in Chapter 5 of “H...

209 12.0

5G-NR LDPC Encoder The Creonic 5G LDPC Encoder IP Core provides a perfect solution for this new LDPC structure with a high level of flexibility while maintaining high th...

210 150.0

Synopsys 1.6T Ethernet MAC IP The Synopsys 1.6T Ethernet MAC IP implements the functions required by the IEEE 802.3-2018 specification to communicate over Ethernet providing a simp...

211 100.0

1.6T Ethernet PCS IP The Synopsys 1.6T Ethernet PCS IP is based on the concepts of the evolving draft IEEE 802.3dj standard creating a flexible system solution for next ge...

212 10.0

10Base-T/100Base-TX Fast Ethernet PHY 10Base-T/100Base-TX Fast Ethernet PHY...

213 0.0

112G Ultra-Low Power VSR PHY in TSMC N5 for optical modules and accelerators Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performan...

214 40.0

LDPC Decoder for 5G NR and Wireless Mobiveil's 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance. It...

215 0.0

VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs ...

216 0.0

100G Ethernet PCS IP The Synopsys 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a complete set of features that enable ...

217 30.0

1.6T Ethernet UMAC CoMira’s 1.6T Ethernet UMAC IP is designed to fulfill the MAC, PCS, and FEC requirements outlined in the IEEE 802.3-2022, IEEE 802.3ck, IEEE 802.3df, ...

218 7.0

Doppler Channel IP Core The Creonic Doppler Channel IP is a Doppler shift frequency (DSF) generator capable of introduce a shift frequency to samples as a phase offset. The I...

219 0.0

16G Ethernet SerDes PHY Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The 16 ...

220 5.0

DiFi IP core The DiFi IP core is a highly scalable and silicon agnostic implementation of the IEEE-ISTO Std 4900-2021: Digital IF Interoperability Standard v1.2.1 ...

221 30.0

LDPC Encoder / Decoder Nand Flash write cycles are limited. An ECC detects and corrects failed operations, increasing the lifetime of the Nand Flash memory. For Nand Flash-b...

222 0.0

Automotive Ethernet (100BaseT1) Whitebox PHY IP with BroadR Reach The Automotive Ethernet PHY IP Core is a 100M Ethernet PHY IP. Boasting a BroadR-Reach™ feature compatible with 100BaseT1 operations. It is a highly i...

223 0.0

Reed Solomon Decoder IP Core A high performance, fully configurable Reed Solomon Decoder IP Core that is intended for use in a wide range of applications requiring forward error c...

224 0.0

Reed Solomon Encoder IP Core A high performance, fully configurable Reed Solomon Encoder IP Core that is intended for use in a wide range of applications requiring forward error c...

225 5.0

IEEE 802.1 Clause 4 MAC The CT25208 Digital IP core is a standard Clause 4 CSMA/CD MAC exposing a proprietary, FIFO-like MAC Client interface (TX/RX). On the other end, th...

226 10.0

UDP/IP Hardware Protocol Stack UDP UDPIP Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...

227 0.0

PWM Pulse Width Modulator The PWM IP core implements a compact and highly flexible Pulse Width Modulator. The core generates a repeated pattern of pulse trains of run-time conf...

228 2.0

MAC Privacy Protection IP The MAC Privacy Protection IP is a fully compliant solution that provides Ethernet Layer 2 Security for port and data privacy as standardized in IEEE ...

229 0.0

Centralized Network Configurator (CNC) for TSN nodes such as endpoints and Switches Centralized Network Configurator or CNC is a component used in Time Sensitive Networking (TSN) networks. The CNC monitors data streams while coordinat...

230 0.118

10/100 Ethernet PHY IP, Energy Efficient, UMC 0.11um HS/AE process 10/100 Base-TX/FX Energy Efficient Ethernet PHY, UMC 0.11um HS/AE (AL Advance Enhancement) Logic process....

231 0.118

10/100 Ethernet PHY IP, UMC 65nm SP process 10/100 Base-TX Fast Ethernet PHY, UMC 65nm SP/RVT Low-K Logic process....

232 0.118

10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process 10BASE-Te/100BASE-TX/100BASE-FX/1000BASE-T Energy Efficient Ethernet PHY; UMC 28nm HPC+ process...

233 3.0

DVB-S2 BCH and LDPC Encoder and Decoder DVB-S2 (Digital Video Broadcast - Satellite 2nd Generation) is an ETSI standard of the second generation for digital data transmission via satellites....

234 0.0

MAC - DMAC - 10/100 Mb Media Access Controller Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. DMAC in cooperation with external ...

235 3.0

MAC - DMAC-RMII - 10/100 Mb Media Access Controller with RMII Our innovative solution is a hardware implementation of media access control protocol defined by the IEEE standard. The DMAC-RMII in cooperation with ...

236 0.118

Ethernet MAC IP, 10/100/1G Ethernet MAC, DMA (Direct Memory Access) function embedded, Soft IP 10/100/1000 Ethernet Controller with AHB bus....

237 0.118

Ethernet MAC IP, 10/100 Ethernet MAC, Soft IP 10/100 Ethernet MAC with MII or RMII (Reduced MII) interface....

238 0.0

10/100/1000 MBit Ethernet MAC The GigaBit Ethernet Media Access Controller (GRETH_GBIT) supports 10/100/1000 MBit speed in both full- and half-duplex operation. The dataflow is han...

239 8.0

1Gbit/s LDPC Decoder and Encoder (WiMedia UWB) The solution from Creonic for data rates of up to 1 Gbit/s offers outstanding efficiency in terms of implementation complexity. John Porter, CTO of Ca...

240 2.0

GMR Release 2 and GMR Release 3 LDPC Decoder GEO-Mobile Radio (GMR) is an ETSI standard for satellite phones. The Creonic GMR Decoder IP core supports the PNB2 burst packets that were added in GM...

241 2.0

IEEE 802.15.3c (60 GHz PHY) Multi-Gbit/s LDPC Decoder The IEEE 802.15 working group specifies standards targeting the wireless personal area network (WPAN). Task group 3 of the working group focuses on hi...

242 2.0

DVB-C2 Receiver (including LDPC and BCH decoder) DVB-C2 (Digital Video Broadcast - Cable 2nd Generation) is an ETSI standard of the second generation for digital data transmission via cable networks....

243 5.0

DVB-RCS2 Turbo Decoder DVB-RCS2 (Digital Video Broadcast - Second Generation DVB Interactive Satellite System) is the latest ETSI standard of the second generation for digit...

244 12.0

Fast Fourier Transform IP Core The Creonic Fast Fourier Transform IP Core implements the Decimation in Frequency - Fast Fourier Transform based on the Cooley-Tukey algorithm. The FF...

245 0.0

CCSDS SCCC Modulator/ Turbo Encoder ...

246 0.0

WiMAX IEEE802.16e Transceiver IP Core The transceiver is designed to be used together with an RF tuner and ADC/ DAC converters. The system has internal state machine to control the operat...

247 0.0

DVB-C2 LDPC/ BCH Decoder IP Core In Digital video broadcasting for cable systems systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes co...

248 0.0

Flash Memory LDPC Decoder IP Core In the Sum Product Algorithm (SPA) for LDPC decoding the messages are sent from the check nodes to bit nodes after the SPA steps which are (for one it...

249 3.0

66/2112 Codec for Cyclic Code (2112,2080) The CEC1-66/2112 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the IEEE 802.3ap (10G Backplane Ethe...

250 0.0

G.9960 LDPC Decoder LDPC-G9660 core provides an efficient implementation of the low-density parity-check (LDPC) forward error correcting (FEC) encoding schemes used in th...