201 10.0

LTE/NR Small Block Lengths Decoder TC5390 is a decoder IP Core compliant with the small block lengths coding scheme for UCI as defined by 3GPP 4G-LTE and 5G-NR specifications. A single ...

202 2.0

56G SerDes Ethernet 56G SerDes IP core supports PAM4 signaling in the range of 25.0-60.0 Gbps using full-rate and half-rate modes with scrambled data. Non-return-to-zero ...

203 70.0

SinglePHY 100BASE-T1 22FDX SinglePHY 100BASE-T1 22FDX is a fully integrated 100BASE-T1 PHY IP solution for flexible customer SoC integration in GLOBALFOUNDRIES® 22FDX®....

204 0.0

Manchester Encoder / Decoder The MAN_CODEC IP Core is a versatile encoder and decoder pair that converts a basic NRZ bitstream into a standard Manchester code and vice-versa. The ...

205 33.0

Low-Latency IP 10G Ethernet MAC LeWiz makes available its ultra low-latency 10G Ethernet MAC for IP licensing - targeting low-latency applications such as those in the financial sect...

206 38.0

10G-400G Ethernet/FiberChannel/FlexO Core The 10G-400G Multi-channel Multi-rate Ethernet/FiberChannel/FlexO Core (OmegaCORE400G_ZX) core from Alphawave is a multi-channel multi-rate Ethernet...

207 5.0

DVB-S2X Wideband LDPC BCH Decoder IP Core The DVB-S2X Wideband LDPC Decoder is a powerful FEC core decoder for Digital Video Broadcasting via Satellite. It implements extensions to the DVB-S2 ...

208 0.0

112G Ethernet PHY IP for TSMC N6 The Synopsys 112G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...

209 0.0

112G LR-Max Ethernet PHY for TSMC N5 Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performan...

210 2.0

SDA OCT V3.0 Encoder and Decoder The Optical Communications Terminal (OCT) Standard was developed by the Space Development Agency (SDA) with the purpose of bringing interoperability a...

211 25.0

LDPC Encoder / Decoder for 3GPP 5G NR Our LDPC encoding and decoding IP for the 3GPP New Radio uplink and downlink data channel includes the entire processing chain, to provide quick and e...

212 25.0

Polar Encoder / Decoder for 3GPP 5G NR Our patented polar encoding and decoding IP for the 3GPP New Radio uplink and downlink includes the entire processing chain, to provide quick and easy...

213 2.0

UltraFast BCH Decoder BCH codes are widely used where bit errors are scattered randomly within the codeword. The Creonic Ultra-fast BCH Decoder is capable of processing an ...

214 2.0

ITU 25G PON LDPC Encoder and Decoder The ITU-T G.9804.2 Recommendation defines the common transmission convergence (ComTC) layer for Higher Speed Passive Optical Networks. As part of the ...

215 0.0

DVB-C Demodulator IP Core The demodulator is designed to be used together with a cable tuner and an analog to digital converter (ADC). The system has an internal state machine ...

216 38.0

FlexE 2.1/2.0/1.1/1.0 SHIM Core The Alphawave FlexE SHIM IP core (FlexE SHIM) is cutting edge solution to the Ethernet application. It integrates seamlessly with Alphawave s MC MAC C...

217 1.0

CCSDS 131.2 Wideband Modulator The Creonic CCSDS high performance modulator performs all tasks of an inner transmitter. The modulator expects SCCC (Serial Concatenated Convolutional...

218 0.0

224G Ethernet PHY IP for TSMC N3E The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...

219 10.0

Reed Solomon Erasure Code Zero latency, low gate count, low power, asynchronous Reed Solomon Code based Erasure code for RAID FEC: The whole operation of encoding and decodi...

220 10.0

Reed Solomon Error Correcting Code ECC RS Code Statistics for different values of `$mm` `$tt` Zero latency, low gate count, low power, asynchronous Reed Solomon Code based Error correct...

221 10.0

BCH Error Correcting Code ECC BCH code statistics for different `$mm` `$tt` Zero latency, low gate count, low power, asynchronous BCH Code based Error Correction FEC: T...

222 5.0

FireCode FEC Zero latency, asynchronous, low power , low gate count FireCode FEC. It detects and corrects 11 bits of burst errors in 2112 bits of received codew...

223 5.0

Hamming Code ECC The RTL is configurable for number of message bits that need ECC protection. Once RTL is generated it is fixed. 1- RTL has no RAMS/ROMS/Flip Flop...

224 10.0

LDPC for 5G DVBS2 802.11 Encoder: - Every H-matrix (out of 102, 51 for BG1, and 51 for BG2 in 5G) has its encoder, which is just a bunch of XOR gates and co...

225 5.0

SPI Serial Peripheral Interface Master/Slave The CC-SPI-AXI is a synthesisable Verilog model of a SPI serial peripheral interface Master/Slave controller. The SPI core can be efficiently implemen...

226 1.0

DVB-S2X Multi-Carrier Demodulator The Creonic DVB-S2X high performance multi-carrier demodulator performs all tasks of an inner receiver while processing up to 36 carriers in parallel....

227 38.0

100G/40G/25G/10G GFP Mappers Alphawave provides a family of GFP-F IP blocks for all applications and size constraints ready for FPGA and ASIC solutions. The family covers single ...

228 0.0

GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in TSMC 28HPC+ For Gigabit 10/100/1000 Ethernet applications, the GPHY is a highly integrated single chip. It is a singleport, IEEE 802.3u/ab compatible, power effic...

229 0.0

GbE (10/100/1000 Base-T) PHY IP, Silicon Proven in SMIC 28SF The GPHY is a highly integrated single chip for Giga 10/100/1000 Ethernet applications with minimal power consumption. It is capable of operating in 1...

230 0.0

Express Serial Peripheral Interface IP Core eSPI controller is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of standard eSPI specification. Through its eSP...

231 0.0

FSPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support) The FSPI is a fully configurable SINGLE, DUAL, QUAD and OCTAL SPI master/slave device, which allows user to configure polarity and phase of serial clo...

232 0.0

Octal SPI Controller – XIP functionality (SINGLE, DUAL, QUAD and OCTAL SPI Bus Controller with Double Data Rate support) and DMA Support Octal SPI master is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of Macronix (MX66LM1G45G) Octal SPI REV.1.0 sp...

233 4.0

Home Plug Green PHY MAC Layer TX/RX ntHPGP_MAC IP core implements “Connectionless CSMA-Only Level-0 CCo“ MAC Layer functionality with Passive Coordination, as detailed in Chapter 5 of “H...

234 0.0

5G-NR LDPC Encoder The Creonic 5G LDPC Encoder IP Core provides a perfect solution for this new LDPC structure with a high level of flexibility while maintaining high th...

235 0.0

Reed Solomon Decoder and Encoder FEC IP Core The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the input message in order to...

236 150.0

Synopsys 1.6T Ethernet MAC IP The Synopsys 1.6T Ethernet MAC IP implements the functions required by the IEEE 802.3-2018 specification to communicate over Ethernet providing a simp...

237 38.0

2.5G to 400G GMP Mappers Alphawave offers GMP (generic mapping procedure) mappers for all data rates specified by the ITU-T G.709. We have GMP mapper which works for 400GE (IE...

238 100.0

1.6T Ethernet PCS IP The Synopsys 1.6T Ethernet PCS IP is based on the concepts of the evolving draft IEEE 802.3dj standard creating a flexible system solution for next ge...

239 0.0

Integrated Secure Element (iSE) for high-end devices with HW isolated secure processing Secure-IC provides integrated Secure Elements (iSE) that can act as trust anchors to protect the security assets of a device. An iSE - also referred a...

240 10.0

10Base-T/100Base-TX Fast Ethernet PHY 10Base-T/100Base-TX Fast Ethernet PHY...

241 0.0

112G Ultra-Low Power VSR PHY in TSMC N5 for optical modules and accelerators Synopsys Multi-Protocol 112G PHY IP is part of Synopsys’ high- performance multi-rate transceiver portfolio for high-end networking and high performan...

242 40.0

LDPC Decoder for 5G NR and Wireless Mobiveil's 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance. It...

243 0.0

VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs ...

244 0.0

VESA DisplayPort 2.0 FEC RX The DisplayPort Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPo...

245 0.0

100G Ethernet PCS IP The Synopsys 100G Ethernet Physical Coding Sublayer (PCS) IP, compliant with the IEEE 802.3 standard, provides a complete set of features that enable ...

246 30.0

1.6T Ethernet UMAC CoMira’s 1.6T Ethernet UMAC IP is designed to fulfill the MAC, PCS, and FEC requirements outlined in the IEEE 802.3-2022, IEEE 802.3ck, IEEE 802.3df, ...

247 0.0

Doppler Channel IP Core The Creonic Doppler Channel IP is a Doppler shift frequency (DSF) generator capable of introduce a shift frequency to samples as a phase offset. The I...

248 25.0

TSN Ethernet Endpoint Controller The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking ...

249 38.0

100G OTN Digital Core The OTL4 core (Optical Transport Lane of OTU4) implements the OTL4 layer function of ITU-T G.709. The OTL4 interface can be used in OTU4 or OTUCn appl...

250 0.0

16G Ethernet SerDes PHY Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging applications The 1...