Design & Reuse
Catalog of SIP Cores
System on Chip design resources
425 IP
251
3.0
High-Performance Lossless Compression Core
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. ...
252
20.0
BCH Encoder / Decoder
The IP-Maker BCH Encoder/Decoder is full featured, easy to use into FPGA and SoC designs. To be easily integrated with the system interface, the IP co...
253
1.0
High Throughput QAM Demapper
This is a high throughput QAM constellation demapper and Log Likelihood Ratio (LLR) bit-metric generator. The core is capable of accepting a new equa...
254
1.0
High Throughput Reed Solomon Decoder
This is a Reed Solomon decoder capable of operating with shortened codewords. The basic mother rate is (N,K) = (255,239) which has 16 parity bytes an...
255
1.0
Medium throughput, compact Reed Solomon decoder
This implementation of a M=8 Reed Solomon decoder has been designed to use a minimum set of resources whilst maintaining a medium throughput and flexi...
256
0.0
Reed-Solomon Memory Protection Codec
The Reed-Solomon IP core provide an alternative to traditional Hamming codecs for memory protection - Error Detection And Correction (EDAC) - function...
257
3.0
Open Source Viterbi Decoder (AXI4-Stream compliant)
Convolutional codes are widely adopted in wireless communication systems for forward error correction. Creonic offers you an open source Viterbi decod...
258
1.0
High-throughput Low-memory Viterbi Decoder
This IP core is available in either normal or high throughput configurations. The normal configuration instances a single fully parallel stage, equiva...
259
1.0
Ultra Low-power, compact Hybrid Viterbi Decoder
This IP core is available with a configurable number of ACS units to suit a range of throughput requirements. The default configuration instances 4 AC...
260
1.0
Serial protocol Interface Slave
The MSPIS IP implements a synchronous a single-chip SPI Slave IP capable of high speed serial data transfer with one SPI master. The MSPIS IP can be ...
261
1.0
SPI Master - EEPROM Controller
The MSPIM IP implements a synchronous a single-chip SPI Master IP capable of high speed serial data transfer with up to 8 SPI slave. The MSPIM IP can...
262
0.0
40G UDP IP Stack
Logic Fruit’s 40G UDP IP Stack implements a hardware protocol stack for UDP/IP, allowing fast communication over a point-to-point connection or LAN....
263
0.0
10G UDP IP Stack
This 10G UDP IP Stack carries out the implementation of a hardware protocol stack for UDP/IP, allowing fast communication over a point-to-point connec...
264
0.0
1G UDP IP Stack
Logic Fruit’s 1G UDP IPⓇ is specialized in data transmission and reception over the internet. The UDP Protocol helps to establish a low-latency and lo...
265
0.0
ETHERNET 10G MAC
The 10G Ethernet MAC core is a thoroughly verified Ethernet Media Access Controller function that interfaces with physical layer devices in an Etherne...
266
4.0
Configurable Reed Solomon Decoder
Highly configurable Reed Solomon Decoder compliant with the requirements of nearly all modern standards using Reed-Solomon error correction....
267
4.0
Configurable Reed Solomon Encoder
A fully configurable Reed Solomon Encoder compliant with the requirements of nearly all modern standards that use Reed-Solomon error correction....
268
4.0
Configurable Viterbi Decoder
Highly configurable Viterbi Decoder compliant with the requirements of nearly all modern standards using Viterbi error correction....
269
4.0
Interleaver / De-interleaver
Configurable interleaving/deinterleaving function that can be used in a wide range of applications that employ channel coding....
270
4.0
Single Channel HDLC Controller
Noesis Technologies ntHDLC single channel High-Level Data Link Controller (HDLC) is a full-duplex transceiver with independent transmit and receive un...
271
4.0
Highly Integrated Reed Solomon Codec
ntRSC_IESS core is a highly integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm. The core supports several ...
272
4.0
ITU G.704 E1 Framer/Deframer
Noesis Technologies ntE1_G704 Framer/Deframer is designed for E1 networks and is compliant with ITU recommendations G.704, G.706, G.732, G.775 and O.1...
273
4.0
ITU G.704 T1 Framer/Deframer
Noesis Technologies ntT1_G704 Framer/Deframer is designed for T1 networks and is compliant with ITU recommendations G.704, G.706, G.732, G.775 and O.1...
274
4.0
Configurable Soft Output Demapper
Noesis Technologies Soft Output Demapper is a structural element of any modern telecom system. The receiver extracts the phase and magnitude of the ca...
275
4.0
Configurable Turbo Product Codec
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the...
276
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY...
277
10.0
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY...
278
10.0
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY...
279
10.0
EA/MZ Modulator Driver 1.25Gb/s to 11.3Gb/s
The PMCC_EAMD12G is designed to directly drive the inputs of EA or MZ Modulators or EML devices at data-rates up-to 11.3Gbps. The driver features prog...
280
0.0
Deserializer 1:32 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain
PMCC_DSER12G is a macro-block designed for robust data/clock recovery and demultiplexing 1:32. The serializer (except 32 bit outputs) is implemented b...
281
0.0
Serializer 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10Ge, XFI, Back Plain
PMCC_SER12G is a macro-block designed for robust 8.5-11.3Gb/s data 32:1 serialization independent on data coding. The serializer (except 32 bit inputs...
282
10.0
Serdes 32:1 for 8.5-11.3Gb/s for SONET/SDH, 10GbE, XFI, Back Plain
PMCC_SERDES12G is a macro-block consisting of a 32:1 serializer and 1:32 deserializer with supporting functions such as CDR, CMU, loop-backs, LOL, LOS...
283
0.0
Fractional N PLL 8.5-11.3GHz in GF N65
PMCC_PLL12GFN is a macro-block designed for synthesizing the frequencies required for fiber optic transceivers and serdes using convenient reference f...
284
6.0
Industry reference DVB-RCS turbo decoder
TC1000 implements the turbo code specified by DVB-RCS for Interactive 2-way satellite systems. This turbo code used offers a very high flexibility in ...
285
6.0
High-Speed Turbo Product Code decoder
TC3404 is a 2D TPC decoder that is optimised for high-speed. A single Core achieves in excess of 200 Mbps user rate with the latest FPGA families (Str...
286
6.0
DVB-S2X decoder
TC4000 is fully compliant with DVB-S2 and DVB-S2X specifications, covering modulations up to 256APSK. It performs I/Q demapping, Block deinterleaver,...
287
6.0
CCSDS turbo decoder
TC6000 is a CCSDS turbo decoder....
288
6.0
China Multimedia Mobile Broadcasting (CMMB) LDPC decoder
TC4300 is a LDPC decoder designed for China Multimedia Mobile Broadcasting (CMMB) specifications. The Core is a stand-alone module, with no external m...
289
6.0
LTE / HSPA turbo decoder
TC1700 is a FEC receiver adressing LTE, LTE-A, WiMAX, HSPA/+, and legacy 3G standard. It cover Rate matching , HARQ combining and turbo decoding. The...
290
6.0
ITU-Ghn LDPC Encoder / Decoder
TC4400 is a LDPC decoder core that is fully compliant with ITU G.hn (wireline home networking) specifications. It support a decoded throughput up to 1...
291
6.0
Viterbi decoder for 3GPP WCDMA and 3GPP-LTE
TC2000 is a flexible Viterbi decoder covering LTE, 3GPP WCDMA and WiMAX 16e/m specifications. Throughput range achieved : 100 to 200 Mbits/s. LTE rate...
292
2.0
Reed Solomon Encoder/Decoder
- The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the input message in order ...
293
3.0
BCH Encoder/Decoder
The binary BCH decoder has four main functional blocks along with memory blocks: 1. Syndrome calculation block: identifies the presence of errors in ...
294
4.0
LDPC Decoder for DVB-T2/T2-Lite
In Digital video broadcasting for terrestrial broadcasting systems, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Chec...
295
2.0
Viterbi Decoder
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors...
296
2.0
CCSDS LDPC
...
297
3.0
19 GHz to 20.25 GHz FMCW Modulator for RADAR
The WEA20SFMCWI22G is an ultra-linear FMCW modulator consisting of 3 integrated PLLs. One PLL provides a high frequency Reference signal and the other...
298
0.0
APB Pulse Width Modulator
The APB PWM Module is a standard APB peripheral that generates a programmable duty cycle output signal. The frequency of the output waveform is eithe...
299
15.0
Fibre-Channel Transceiver
SMS3000 is a fully integrated CMOS transceiver compliant with ANSI X3T11 Fiber Channel standards. It contains all necessary Clock synthesis, Clock Rec...
300
20.0
Gigabit Ethernet For Fiber & STP/COAX Transceiver PHY
Gigabit Ethernet Transceiver for Fiber, Short Length Copper, STP and COAX....