351 0.0

Ethernet 2.5G MAC IP SmartDV’s Ethernet 2.5G MAC IP Core is a silicon-proven, high-performance solution designed for a wide range of networking applications including indu...

352 0.0

Ethernet 2.5G PCS IP SmartDV’s Ethernet 2.5G PCS (Physical Coding Sublayer) IP Core is a silicon-proven solution that bridges the Ethernet MAC and PHY layers to ensure rel...

353 0.0

Ethernet 2.5G TSN MAC IP SmartDV’s Ethernet 2.5G TSN (Time-Sensitive Networking) MAC IP Core delivers deterministic, low-latency communication for time-critical applications s...

354 0.0

Ethernet 200G PCS IP SmartDV’s Ethernet 200G PCS (Physical Coding Sublayer) IP Core delivers the critical encoding, alignment, and error correction functions required for ...

355 0.0

Ethernet 400G PCS IP SmartDV’s Ethernet 400G PCS (Physical Coding Sublayer) IP Core is engineered for ultra-fast, high-reliability data transmission in modern networking a...

356 0.0

Ethernet 50G TSN MAC IP SmartDV’s Ethernet 50G TSN (Time-Sensitive Networking) MAC IP Core combines 50G Ethernet throughput with deterministic networking features to meet the...

357 0.0

Ethernet 800G MAC IP SmartDV’s Ethernet 800G MAC IP Core is a high-throughput, feature-rich solution built to support next-generation data communication needs across AI/ML...

358 0.0

Ethernet 800G PCS IP SmartDV’s Ethernet 800G PCS (Physical Coding Sublayer) IP Core is engineered to deliver robust and efficient data encoding, alignment, and error corre...

359 0.0

Synopsys High Speed Ethernet PCS IP up to 200G The Synopsys Ethernet 400G and 200G Physical Coding Sublayer (PCS) IP is compliant with the IEEE 802.3bs standard and provides a complete set of featu...

360 0.0

10Base-T/100Base-TX/1000Base-T Gigabit Ethernet PHY IP （GPHY） in TSMC40 Provides Gbit Ethernet PHY that supports 10M/100M/1000M Base-T and can be applied in Ethernet related scenarios. It can be independently taped out, su...

361 0.0

UALink DL he Chip Interfaces UA Link DL IP Core is a high-performance, silicon-agnostic and fully compliant Data Layer implementation of UALink_200 specifi cati...

362 0.0

UALink TL The Chip Interfaces UA Link TL IP Core is a high-performance, silicon-agnostic and fully compliant Transaction Layer implementation of UALink_200 spec...

363 35.0

50G PON LDPC Mobiveil’s 50G PON LDPC Encoder/Decoder offers industry-leading LDPC error correction in a low-power, small-footprint, high-reliability solution. LDPC...

364 20.0

100Base-T1 Automotive Ethernet PHY 100Base-T1 Automotive Ethernet PHY...

365 0.0

UDP/IP 400G Hardware Protocol Stack UDP UDPIP Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...

366 0.0

Synopsys High Speed Ethernet Dual 800G MAC IP The Synopsys 100G/200G/400G/800G Ethernet MAC IP implements the full MAC layer and reconciliation sublayer compliant with the IEEE 802.3 specification...

367 5.0

BCH Decoder A highly configurable hardware IP core that performs error detection and correction using Bose–Chaudhuri–Hocquenghem (BCH) codes. It detects and corre...

368 5.0

BCH Encoder A fully parameterizable SystemVerilog IP core implementing systematic encoding for binary BCH (Bose-Chaudhuri-Hocquenghem) codes. The core supports ar...

369 0.0

Ethernet MAC 100G/200G/400G/800G/1.6T The Chip Interfaces 100G/200G/400G/800/1.6T Ethernet Media Access Control (MAC) IP core provides a comprehensive and flexible solution for implementin...

370 0.0

Ethernet PCS 100G/200G/400G/800G/1.6T Chip Interfaces 100G-1.6T Ethernet PCS IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) described in the Ethernet st...

371 0.0

Ultra Ethernet MAC & PCS 100G/200G/400G/800G The Chip Interfaces Ultra Ethernet MAC & PCS IP core delivers a complete, silicon-agnostic implementation of the Ultra Ethernet Transport link layer, ...

372 0.0

16G Ethernet SerDes PHY Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The 16 ...

373 0.0

Industry's first complete L1+L2 Ethernet IP solution for AI scale-up networks, aligned to OCP ESUN 1.0 spec The Synopsys Ethernet for Scale-Up Networking (ESUN) IP solution, is the industry’s first complete Layer 1 and Layer 2 IP offering purpose-built for E...

374 5.0

Ethernet MAC 10G SFP The ETH_MAC_10G_SFP IP incorporates one Ethernet MAC at 10Gbits on a FPGA and is compliant with IEEE802.3ae specification. It is designed to be con...

375 0.3729

A bridge to convert the slave SPI interface to the master I2C interface and vice versa The dti_spi_to_i2c is a bridge to convert the slave SPI interface to the master I2C interface and vice versa....

376 0.3729

A bridge to convert the slave SPI interface to the master UART interface and vice versa The dti_spi_to_uart is a bridge to convert the slave SPI interface to the master UART interface and vice versa....

377 1.0

Gigabit Ethernet MAC with AVB The Arasan Gigabit Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3-2008 standard. In addition, the Gigabit Ethernet MAC...

378 5.0

HDLC - DHDLC - HDLC/SDLC controller The DHDLC IP core is used for controlling HDLC/SDLC transmission frame, designed to be used with 8-bit MCU, like DP8051/DP80390. It allows to save MCU...

379 5.0

DMESCC - Enhanced Multiprotocol Serial Communication Controller The DEMSCC – Dual channel Multiprotocol Enhanced Serial Communication Controller, is designed for use with 8- and 16- bit microprocessors. The DMESCC...

380 0.0

224G Ethernet PHY for TSMC 3nm The Synopsys 224G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency need...

381 10.0

Gigabit Ethernet PHY Gigabit Ethernet PHY (in production)...

382 10.0

Gigabit Ethernet PHY Gigabit Ethernet PHY...

383 10.0

Gigabit Ethernet PHY (Modification Right) Gigabit Ethernet PHY Modification Right (in production)...

384 10.0

100G UDP/IP Hardware Protocol Stack UDP UDPIP Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...

385 10.0

10Base-T/100Base-TX Fast Ethernet PHY 10Base-T/100Base-TX Fast Ethernet PHY...

386 10.0

Gigabit Ethernet PHY Gigabit Ethernet PHY...

387 6.0

LTE turbo decoder TC7000-LTE is a convolutional turbo code (CTC) decoder optimized for FPGAs. Its unique pipe-line architecture enables to reach very high clock frequen...

388 6.0

High Performance Turbo Code TC1600 is ideally suited for applications requiring small to medium block sizes in order to reduce latency and offer a high physical layer flexibility...

389 6.0

Gigabit-range, low complexity LDPC decoder TC4902 is ideally suited for applications requiring a very efficient throughput/area ratio, while not sacrificing SNR performance. TC4902 implements a...

390 6.0

DVB-RCS2 turbo decoder TC1620 is a high performance turbo decdoer Core compliant with DVB-RCS2 specifications. Ideally suited fo systems requiring flexibility, short/medium ...

391 6.0

LTE Cat-0 turbo decoder TC1770 is a IoT-optimized turbo decoder Core compliant with LTE Cat-0 / Cat-M (release 12 and release 13). This Core incorporates LTE rate matching an...

392 6.0

Flexible LDPC encoder/decoder TC5100 is a highly flexible LDPC encoder/decoder Core. It can essentially cover all possible quasi-cyclic LDPC codes: WiFi, WiMAX, proprietary codes, ...

393 6.0

LTE / WiFi Viterbi decoder TC1720 is a high throughput and low latency Viterbi decoder optimized for WiFi and LTE applications. It covers optionally also WCDMA specifications....

394 10.0

10G / 25G UDP/IP Hardware Protocol Stack UDP UDPIP Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...

395 6.0

5G LDPC Encoder / Decoder TC5200 is an efficient LDPC encoder/decoder Core solution fully compliant with 3GPP NR (5G) specifications. The Core is fully validated and has been s...

396 6.0

5G Polar encoder/decoder TC5300 is an efficient Polar encoder/decoder Core solution compliant with 3GPP NR (5G) specifications. The Core is fully validated and has been select...

397 10.0

NR-5G Polar Decoder and Encoder IP Core The Forward Error Correction (FEC) sub-system is one of the essential basing blocks in any communication systems so a powerful FEC code is needed. The...

398 0.0

High-Performance Lossless Compression Core Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. ...

399 3.0

100G Reed-Solomon Codec for Ethernet IEEE 802.3 Clause 91 (803.3bj) The RS100-160 core implements the codec for the Forward Error Correction (FEC) cyclic code RS(528, 514, 7,10) used in the IEEE 802.3bj (100G Backplane...

400 10.0

1G IP/UDP full HW Stack Transmitter / Receiver To efficient transfer large amount of data and off-load the system processor, BitSim has launched its IP, Bit-UDP Ethernet. This core is a real-tim...