Design & Reuse
Catalog of SIP Cores
System on Chip design resources
1205 IP
251
7.0
12 Bit 20 MS/s Pipeline ADC
This pipelined ADC can be applied for up to 20MSps sampling frequencies. By using interleaved switched-capacitor circuitries a CLK signal with half ...
252
7.0
12 Bit 40 MS/s Pipeline ADC
This pipelined ADC can be applied for up to 40MSps sampling rates with on-chip track&hold block or continuous signal sampling....
253
7.0
12 Bit 54 kS/s Cyclic ADC
This cyclic ADC, based on redundant-signed-digit (RSD) conversion, is optimized for power efficiency and high accuracy. It provides 12 bit resolution ...
254
7.0
12-Bit 1 MS/s DAC with voltage output
The IP consists of a 12 bit current steering DAC. The DAC is connected to a transimpedance amplifier(TIA) in order to provide a voltage output signal....
255
7.0
15 Bit 192 kS/s Sigma-Delta ADC
The ADC IP is a general-purpose sigma-delta converter and it is configurable for conversion speed and power consumption with adaptable oversampling ra...
256
7.0
15 Bit 8 kS/s Sigma-Delta ADC
The ADC IP is a general-purpose sigma-delta converter and it is configurable for conversion speed and power consumption with adaptable oversampling ra...
257
7.0
16 Bit 10 kS/s Incremental Delta - Sigma ADC
On the one hand, incremental delta-sigma modulators are able to convert DC and multiplexed input signals as known from Nyquist ADCs. On the other hand...
258
7.0
16 Bit 13 kS/s Cyclic ADC
This cyclic ADC, based on redundant-signed-digit (RSD) conversion, is optimized for power efficiency and high accuracy. It provides 16 bit resolution ...
259
7.0
Ultra-Low Power 6 - 13 Bit 0.5 -10 kS/s 10μW Analog Front End
The Analog-Frontend (AFE) IP consists of programmable current and voltage preamplifier followed by a Successive Approximation Register (SAR) architect...
260
7.0
Ultra-Low Power 6 - 13 Bit 1-10 kS/s 1.9 μW SAR ADC
The IP consists of a Successive Approximation Register (SAR) architecture ADC using charge-redistribution technique. The ADC IP is configurable regard...
261
7.0
Ultra-low power RF receiver / WakeUp receiver
The integrated ultra-low power receiver technology RFicient® was developed for ISM frequency bands and built in standard CMOS technology. The receiver...
262
7.0
USB 2.0 Full/Low-Speed Device Core
The FHG USB DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-speed USB 2.0 device functionality wi...
263
7.0
USB 2.0 Full/Low-Speed Embedded Host Controller
The FHG USB EHC is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-/low-speed USB 2.0 host functionality ...
264
7.0
USB 2.0 High/Full-Speed Device Core
The FHG USB2 DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high-/full-speed USB 2.0 device functiona...
265
7.0
USB 2.0 High/Full/Low-Speed Embedded Host Controller
The FHG USB2 EHC is a scalable, high performance IP-module for usage in ASIC and FPGA designs to integrate high/full/low-speed USB 2.0 host functiona...
266
7.0
USB 2.0 OTG Full/Low-Speed Dual Role Core
The FHG USB OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-/low-speed USB 2.0 device and host ...
267
7.0
USB 2.0 OTG High/Full/Low-Speed Dual Role Core
The FHG USB2 OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high/full/low-speed USB 2.0 device and ...
268
6.0
Warping Engine IP block for image transformation, HUDs and fish-eye correction
TES Warping Engine is a specialized IP core for arbitrary high-performance re-mapping of bitmaps from memory-to-memory or memory-to-stream. Applicatio...
269
6.0
Passive/active NFC transceiver, Silicon Proven supports ISO 14443-A, 14443-B, and 15693 standards
CSEM’s NFC Tag IP is a high-performance, energy-efficient solution designed for integration into Proximity Integrated Circuit Cards (PICC) and Vicinit...
270
6.0
Viterbi decoder for 3GPP WCDMA and 3GPP-LTE
TC2000 is a flexible Viterbi decoder covering LTE, 3GPP WCDMA and WiMAX 16e/m specifications. Throughput range achieved : 100 to 200 Mbits/s. LTE rate...
271
6.0
Multi spectral CMOS image sensor for NIR, Xray and Visible imaging
SWISSMODICS is a state-of-the-art multi-spectral image sensor IP , designed for embedded structural health monitoring, non-destructive inspection, mul...
272
6.0
Multi-Channel ECG, EEG, and EMG Analog Front Ends (AFEs)
CSEM’s multi-channel analog front ends (AFEs) are designed for high-precision acquisition of biopotential signals such as ECG, EEG, and EMG. These AFE...
273
6.0
PVT - Process, Voltage, and Temperature Monitor
The ODT-PVT-ULP-001C-12 is an ultra-low power temperature, voltage and process monitor designed in a 12nm CMOS process. This IP operates over the enti...
274
6.0
PVT - Process, Voltage, and Temperature Monitor
The ODT-PVT-ULP-001C-3 is an ultra-low power temperature, voltage and process monitor designed in a 3nm CMOS process. This IP operates over the entire...
275
6.0
PVT - Process, Voltage, and Temperature Monitor
The ODT-PVT-ULP-001C-22FDX is an ultra-low power temperature, voltage and process monitor designed in a 22nm CMOS process. This IP operates over the e...
276
5.1304
IEEE 802.16e WiMax Turbo Encoder and Decoder IP Core
This IP suite implements the WiMax (IEEE 802.16e-2009) Convolutional Turbo Code (CTC) in hardware. The Turbo Encoder performs Forward Error Correction...
277
5.1304
3GPP 5G NR and Wi-Fi 7 LDPC Encoder Decoder IP
LDPC Encoder/Decoder core provides a high-performance implementation of the Low-Density Parity-Check (LDPC) with the 3GPP 5G NR (TS 38.212), 3GPP RedC...
278
5.1304
3GPP LTE Turbo Encoder and Decoder IP Core
This IP suite implements the 3GPP LTE (3GPP TS 36.212 1) Convolutional Turbo Code (CTC) in hardware. The Turbo Encoder performs Forward Error Correcti...
279
5.0
100 Gbit/s IEEE 802.3bj RS Encoder and Decoder
IEEE 802.3bj was developed in response to the rapid growth of server, network and internet traffic. The standard meets the need for higher data rates ...
280
5.0
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
The 32-bit A45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compr...
281
5.0
64-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
The 64-bit AX45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit comp...
282
5.0
64-bit CPU with Modern RISC Architecture, MemBoost and PMA
The 64-bit AX27 is a 5-stage processor that supports the latest RISC-V specification, including "G" ("IMAFD") standard instructions, "C" 16-bit compre...
283
5.0
16-Bit Sigma-Delta CODEC (ADC & DAC) with headset, handset and 400mW Speaker Amplifier, DBHitek 0.11um
The AR34P2A specifies a mass-production proven, low power mono audio CODEC IP for multimedia audio / voice phone system. The IP employs multi-bit sigm...
284
5.0
Ka-Band beamforming and transceiver ASIC platform
The ENS92030 is a versatile multi-channel, Ka-Band frequency, beamforming transceiver IC for phased-array electronically steerable antenna systems. ...
285
5.0
Radiation-Hardened GPIO, ODIO and LVDS Interface in SkyWater 90nm
This Library, developed on SkyWater 90nm CMOS, delivers a radiation-hardened suite of robust interfaces covering general-purpose, open-drain, and high...
286
5.0
DCRP1A - 100% Secure Cryptographic System for RSA, Diffie-Hellman and ECC with AMBA AHB, AXI4 and APB
The CryptOne, a 100% secure cryptographic system, has been based on more than 20 years DCD’s market experience. Starting from 1999, Digital Core Desig...
287
5.0
CCSDS 231.0 LDPC Encoder and Decoder
The CCSDS 231.0 LDPC IP supports the LDPC coding schemes as defined by the CCSDS standard. The LDPC codes with rate 1/2, coded block lengths 128 and 5...
288
5.0
CCSDS SCCC Turbo Encoder and Decoder
The recommended CCSDS 131.2-B-1 standard introduces a Serial Concatenated Convolutional Code (SCCC). Main goal of this code is to allow an efficient u...
289
5.0
DDR3/4 and LPDDR2/3/4/4x Combo PHY&MAC
With sophisticated architecture and advanced technology, this DDR3/4 and LPDDR2/3/4/4x IP combo solution with high performance and low power. In 12~28...
290
5.0
IEEE802.11n/ac/ax Wi-Fi LDPC Decoder and Encoder IP Core - silicon proven
The 802.11n/ac/ax LDPC decoder is developed for high throughput WLAN applications....
291
5.0
Temperature Sensor with Digital Output (High accuracy thermal sensing for reliability and optimisation), TSMC 28HPC+
A high precision low power junction temperature sensor that has been developed to be easily embedded into digital ASIC designs. The block features an ...
292
5.0
Temperature Sensor with Digital Output (High accuracy thermal sensing for reliability and optimisation), UMC 14FFC
A high precision low power junction temperature sensor that has been developed to be easily embedded into digital ASIC designs. The block features an ...
293
5.0
SHA-384 and SHA-512 Secure Hash Crypto Engine
The SHA-384/512 is a high-throughput, and compact hardware implementation of the SHA-384 and the SHA-512 cryptographic hash functions provisioned by t...
294
5.0
High-performance Processor for Real-time and Linux Applications
The Andes Technology N13 processor is a high performance CPU core architected for computation intensive applications running either on operating syste...
295
5.0
Electro-Magnetic Fault Injection (EMFI) Detector analog anti-tamper add-on for Root of Trust and PUF
The agileEMSensor product is a latch based sensor designed to detect electromagnetic disturbances in critical circuits. It provides security and prote...
296
5.0
Elliptic Curve Digital Signature generation and verification
eSi-ECDSA is a hardware acceleration core for Elliptic Curve (EC) Digital Signature Algorithm modular arithmetic operations defined in IEEE1363 and ot...
297
5.0
Clock Attack Monitor analog anti-tamper add-on for Root of Trust and PUF
The agileCAM is a Ring Oscillator (RO) based clock attack monitor designed to detect clock attacks due to violation of the set-up time requirements of...
298
5.0
VME Slave Controller, bridging VME bus and local bus
The VMESmodule is a complete VME Slave Controller core providing a bridge between the VME bus and the local bus. The core contains a VME Slave, a VME ...
299
5.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF PLUS LL
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
300
5.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FFC NS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...