Design & Reuse
2081 IP
1751
0.118
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT
UMC 55nm ULP process , Single-Port SRAM with row repair and HVT...
1752
0.118
One Port Register File Compiler IP, Bit-cell: 0.425um2 (HVT), Support retention and deep sleep modes with built-in power gating circuitry., UMC 55nm LP process
UMC 55um LP Low-K process One Port Register File compiler....
1753
0.118
Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process
Input 25M~440MHz, output 267M-533M, 200M-400M and 160M-320M, frequency synthesizable PLL; UMC 40nm LP/RVT Logic Process...
1754
0.118
Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process.
Input 2MHz~16MHz, output 16~72MHz and 72MHz~200MHz, 1.08~1.32V PLL; UMC 55nm Low Power Process....
1755
0.118
Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Input 32.768KHz, Ouput 12 and 24MHz PLL, UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
1756
0.118
Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process
Input 32.768KHz, Output 12 and 48MHz PLL; UMC 55nm LP/RVT Logic Process...
1757
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process.
Input 333M-1600MHz, output 333M-1600MHz, all digital DLL for DDR4 SDRAM controller usage, supports slave delay line to generate 25%/50%/100% delay in ...
1758
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 100% delay in period of FREF,UMC 28nm Logic and Mi...
1759
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 25% delay in period of FREF,UMC 28nm Logic and Mix...
1760
0.118
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPC Process
Input 333M-1600MHz, output 333M-1600MHz, all digital slave delay line of FXADDLL340HJ0C to generate 50% delay in period of FREF,UMC 28nm Logic and Mix...
1761
0.118
Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process
Input 6M-27M Hz, output 10M-850M Hz, frequency synthesizable PLL; UMC 40nm Logic LP RVT and LVT process...
1762
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 100% delay in period of FREF,UMC 28nm Logic and Mi...
1763
0.118
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mixed-Mode HPM Process
Input 800M-1600MHz, output 800M-1600MHz, all digital slave delay line of FXADDLL340HJ0G to generate 50% delay in period of FREF,UMC 28nm Logic and Mix...
1764
0.118
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process.
Input 80MHz-440MHz, DQS delay 1/32 and 1/16 of FREF period, UMC 40nm LP/RVT Low-K logic process....
1765
0.118
Intelligent Energy Controller for voltage and frequency scaling.
Intelligent Energy Controller for voltage and frequency scaling....
1766
0.118
Internal-RC and Built-in Bandgap, trimmable fixed frequency 12MHz. Input 1.14V-1.26V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process
Internal-RC and Built-in Bandgap, trimmable fixed frequency 12MHz. Input 1.14V-1.26V; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...
1767
0.118
Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process.
Voltage mode 10/100 Base-TX/FX Energy Efficient Ethernet PHY; Support EtherCAT and cable diagnostic; UMC 0.11um HS/AE Logic Process....
1768
0.118
compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process .
compensation block for FXDDR3LTA102HH0L and FXDDR3LTD102HH0L,UMC 40nm LP/RVT LowK Logic Process ....
1769
0.118
Source and Sink Current 100mA LDO for 28nm cascade I/O, UMC 28nm HPC Logic and Mixed-Mode Process
Source and Sink Current 100mA LDO for 28nm cascade I/O, UMC 28nm HPC Logic and Mixed-Mode Process...
1770
0.118
Power Management Unit(5-sets DC-DC, 2-sets REG, PowerSwitch, and Li-ion Charger) for Audio Platform; UMC 0.35um 3.3V/5V CDMOS process
Power Management Unit(5-sets DC-DC, 2-sets REG, PowerSwitch, and Li-ion Charger) for Audio Platform; UMC 0.35um 3.3V/5V CDMOS process...
1771
0.118
Power Management Unit(5-sets DC-DC, 2-sets REG, PowerSwitch, and Li-ion Charger) for Audio Platform; UMC 0.35um 3.3V/5V CDMOS process
Power Management Unit(5-sets DC-DC, 2-sets REG, PowerSwitch, and Li-ion Charger) for Audio Platform; UMC 0.35um 3.3V/5V CDMOS process...
1772
0.118
APB Fundamental Peripheral IP, Serial Interface controller for multiple frame formats, SSP (by TI), SPI (by Motorola), Microwire (by NS), I2S (by Philips), AC - link (by Intel) and SPDIF (by Intel), Soft IP
Synchronous serial port interface controller with APB interface....
1773
0.118
USB3.0 OTG controller with AXI interface, support Host, Peripheral and OTG function
USB3.0 OTG controller with AXI interface, support Host, Peripheral and OTG function...
1774
0.118
FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer rate. This IP is compliant with the V-By-One HS Standard, Ver. 1.3. It transfers the packed packet from direct the video stream
FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer rate. This IP is compli...
1775
0.118
FXAFE030HH0L is an Analog Front End IP for image processing applications. FXAFE030HH0L is fabricated in UMC 40 nm logic LP/HVT Low-K process to implement a signal processing solution for scanners, video and imaging applications. _x005F_x005F_x005F_x000D_
FXAFE030HH0L is an Analog Front End IP for image processing applications. FXAFE030HH0L is fabricated in UMC 40 nm logic LP/HVT Low-K process to implem...
1776
0.118
AXI system Peripheral IP, DMA controller for AXI master port and slave port (32 - bit, 64 - bit and 128 - bit), 8 channels DMA, Soft IP
DMA controller with AXI interface....
1777
0.0
1 to 20 MHz Phase-frequency detector and charge pump
Phase-frequency detector (PFD) forms a control signal for VCO tuning. PFD compares phases of a divided VCO signal and a divided reference oscillator s...
1778
0.0
3 to 5 GHz LNA with 2.8dB NF and 20dB gain
130iHP_LNA_04 consists of two bipolar amplifier stages. The block is used correction circuit for frequency range extension. Amplifier output based on ...
1779
0.0
8 track thick oxide standard cell library at TSMC 130 - low leakage and direct battery connection (operating voltages from 1.08 V to 3.63 V)
TSMC 130 G, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the ...
1780
0.0
9 track thick oxide standard cell library at TSMC 180 - low leakage and direct battery connection (operating voltages from 1.62 V to 3.63 V)
TSMC 180 RF, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the...
1781
0.0
9 track thick oxide standard cell library at TSMC 180 - low leakage and direct battery connection (operating voltages from 1.62 V to 3.63 V)
TSMC 180 G, SESAME BIV, a new thick oxyde based standard cell library for ultra low leakage logic design and/or direct battery connection through the ...
1782
0.0
1-56G-PCIe Gen5 ePHY Multi-Protocol SerDes IP - 7nm Low Power and Latency
Ultra-high speed SerDes IP, adopted by global Tier-1 network/storage/5G OEMs and major semiconductor companies. eTopus is the pioneer on PAN4 ADC/DSP...
1783
0.0
2-cluster Power Consumption & Performance Efficiency Enhanced Series6XT 3D/2D/Compute GPU including OpenGL ES 3.0, DX10_0 Feature Level and OpenCL Support , 10-bit YUV, YUV framebuffer, ASTC
The PowerVR Series6XT family is based on the Rogue architecture, includes GPUs ranging from two to six clusters and builds on the previous Series6 fam...
1784
0.0
4-cluster Power Consumption & Performance Efficiency Enhanced Series6XT 3D/2D/Compute GPU including OpenGL ES 3.0, DX10_0 Feature Level and OpenCL Support, 10-bit YUV, YUV framebuffer, ASTC
The PowerVR Series6XT family is based on the Rogue architecture, includes GPUs ranging from two to six clusters and builds on the previous Series6 fam...
1785
0.0
2-cluster Series6XT 3D/2D/Compute GPU including OpenGL ES 3.0, DX10_0 Feature Level and OpenCL Support , 10-bit YUV, YUV framebuffer
The PowerVR Series6XT family is based on the Rogue architecture, includes GPUs ranging from two to six clusters and builds on the previous Series6 fam...
1786
0.0
v-MP6000UDX - Deep Learning and Vision Processor
The videantis processor is the most power-efficient and highest-performing visual processing architecture that you can license on the market. Whether ...
1787
0.0
0.1 to 150 MHz LNA with 5 dB NF and 57 dB gain
065TSMC_LNA_09 is used to amplify signal from the radio receiver input in band up to 150MHz. LNA has a low noise figure, high linearity and wide gain ...
1788
0.0
1.12V/10uA, 20uA, 30uA, 50uA, 100uA Reference current and voltage source with temperature sensor
065TSMC_RS_03 is a reference current and voltage source (RS), used to supply analog blocks. It is based on bandgap reference voltage source, forming t...
1789
0.0
1.16 to 1.26 and 1.56 to 1.61 GHz low noise amplifier with 27.5dB gain
350AMS_LNA_04 is a common receiver front-end device which is used to provide impedance matching to off-chip circuits and to perform first step low noi...
1790
0.0
1.17 V Reference current and voltage source
Reference current and voltage source is used to supply any analog blocks. It is based on the reference voltage source forming temperature compensation...
1791
0.0
1.18 V/ 1.02...5.1 uA Reference current and voltage source
Reference current and voltage source is used to supply any analog blocks. It is based on the reference voltage source forming temperature compensation...
1792
0.0
1.22V/1uA Reference voltage and current source
180XFAB_RS_01 consists of a bandgap reference voltage regulator, formed temperature and power supply variations independent voltage and bias, formed r...
1793
0.0
H.264/265 Video Encoder and Decoder IP
The Hardware Encoder Video Accelerator (HEVA), supports HEVC encoding low complexity with a flexible architecture targeting at least 1080p60 with mini...
1794
0.0
0.6V/10, 20uA Reference voltage and current source
055TSMC_RS_02 consists of bandgap voltage reference and two voltage-to-current converters: one of them is based on external resistor and thus could be...
1795
0.0
0.6V/10u, 20uA, 100nA, 200nA Reference voltage and current source
055TSMC_RS_05 is a reference voltage and current source that consists of bandgap voltage reference, two voltage-to-current converters and current-volt...
1796
0.0
1.8V to 3.3V GPIO and 3.3V LVDS in Skywater S90-LN
This I/O Library is a robust, mixed-signal I/O platform developed for the SkyWater 90 nm (S90-LN) process, designed to support reliable SoC integratio...
1797
0.0
5/10/40G Ultra Low Latency MAC PCS with AXI-4 and UCIe support
This IP is optimized for AI/ML workloads and lowest possible latency.It is not meant to be a generic 1G to 10G MAC – it only supports 5G and 10G...
1798
0.0
5/10/40G Ultra Low Latency MAC PCS with AXI-4 and UCIe support
This IP is optimized for AI/ML workloads and lowest possible latency. It is not meant to be a generic 1G to 10G MAC – it only supports 5G and 10G ope...
1799
0.0
10/12-bit Extended and 8-bit Baseline JPEG Image & Video Decoder
The JPEG-D-X core from Alma Technologies is a standalone and high-performance JPEG decoder for still image and video compression applications. Complia...
1800
0.0
100 dB of SNR, 24-bit stereo audio CODEC with 8 ADC paths, an embedded regulator and headphone/line-out driver in TSMC 55uLP
sCODa95-H1-LR_08.TSMC.55.ULP is a feature-rich audio CODEC in TSMC 55uLP which provides the insurance of the best sound quality after integration into...