Design & Reuse
2081 IP
251
0.0
PVT Sensor - TSMC 40
1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...
252
0.0
PVT Sensor - TSMC 7FF
1-VIA’s PVT Sensor is a highly integrable macro for monitoring process, voltage and temperature variation on-chip. It consumes ultra-low power in miss...
253
0.0
PVT sensor in 28nm
Process voltage and temperature detection of the silicon chip die is accomplished by PVT Sensor, an IP. It offers special characteristics like tempera...
254
0.0
PVT sensor integrated SAR ADC in 12nm
PVT Sensor & SAR ADC is an IP Core including TEMSEN ,.SARADC and 3xPOR. The SAR ADC used in this system offers a 10-bit resolution, ensuring precise a...
255
0.0
PVT Sensor(SF 4nm, LN04LPP)
The PVT sensor indicates the junction temperature as a 12-bit binary digital code. It contains a main sensor, remote probes and an Analog-to-Digital...
256
60.0
MIPI I3C PHY - TSMC (12nm, 7nm, 5nm, and 22nm) - GF 12nm
The I3C bus (incl. PHY) is used for various sensors in the mobile/automotive system where the Host transfers data and control between itself and vario...
257
50.0
UFS 4.0 Host Controller compatible with M-PHY 5.0 and UniPro 2.0
The Arasan UFS Host -UniPro IP is a simple, high performance, serial interface used primarily in mobile systems between host processing and NVM mass s...
258
44.0
FlexNoC 5 Option For Scalability and Performance Critical Systems
Arteris IP FlexNoC Performance Option accelerates development of next-generation deep neural network (DNN) and machine learning systems. Automate and ...
259
40.0
UFS 3.0 Host Controller with AES Encryption compatible with M-PHY 4.0 and UniPro 1.8
Arasan's Universal Flash Storage 3.0 (UFS 3.0) is a simple but high performance, serial interface primarily used in mobile systems, between host proce...
260
30.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-NS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
261
20.0
10 Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto
The 10 Gigabit Ethernet Media Access Controller with IEEE 1588 PTP IP core is compliant to the Ethernet/IEEE 802.3-2008 standard and has hardware bas...
262
14.0
10Gbps Multi-Link and Multi-Protocol PCIe 3.1 PHY IP for TSMC
Silicon-proven PHY for PCIe, USB, Ethernet, DisplayPort, and other protocols The Cadence® 10Gbps Multi-Link and Multi-Protocol PHY IP provides a flex...
263
10.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF PLUS LL
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
264
10.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FFC NS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
265
10.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28 HPC-EW
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
266
10.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPC PLUS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
267
10.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 40LP-EW
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
268
8.0
FortifyIQ's Secure Hybrid Crypto Box IP Core with Classical and Post-Quantum Cryptography for Embedded Systems (AES, HMAC-SHA2, ECC/RSA etc., PQC) (SCA,DPA,FIA secure)
FortifyIQ’s Hybrid Crypto Box IP core is a comprehensive, high-efficiency cryptographic solution that combines RSA, ECC, AES, and SHA-2/HMAC with a bu...
269
7.0
10 Bit 40 MS/s Pipeline ADC
The IP consists of a 10 bit 40 MS/s pipeline ADC. A time-interleaved architecture with 1.5 bit per stage is used. The operational amplifiers are share...
270
7.0
12 Bit 17 kS/s Cyclic ADC
This cyclic ADC, based on redundant-signed-digit (RSD) conversion, is optimized for power efficiency and high accuracy. It provides 12 bit resolution ...
271
7.0
12 Bit 20 MS/s Pipeline ADC
This pipelined ADC can be applied for up to 20MSps sampling frequencies. By using interleaved switched-capacitor circuitries a CLK signal with half ...
272
7.0
12 Bit 40 MS/s Pipeline ADC
This pipelined ADC can be applied for up to 40MSps sampling rates with on-chip track&hold block or continuous signal sampling....
273
7.0
12 Bit 54 kS/s Cyclic ADC
This cyclic ADC, based on redundant-signed-digit (RSD) conversion, is optimized for power efficiency and high accuracy. It provides 12 bit resolution ...
274
7.0
12-Bit 1 MS/s DAC with voltage output
The IP consists of a 12 bit current steering DAC. The DAC is connected to a transimpedance amplifier(TIA) in order to provide a voltage output signal....
275
7.0
15 Bit 192 kS/s Sigma-Delta ADC
The ADC IP is a general-purpose sigma-delta converter and it is configurable for conversion speed and power consumption with adaptable oversampling ra...
276
7.0
15 Bit 8 kS/s Sigma-Delta ADC
The ADC IP is a general-purpose sigma-delta converter and it is configurable for conversion speed and power consumption with adaptable oversampling ra...
277
7.0
16 Bit 10 kS/s Incremental Delta - Sigma ADC
On the one hand, incremental delta-sigma modulators are able to convert DC and multiplexed input signals as known from Nyquist ADCs. On the other hand...
278
7.0
16 Bit 13 kS/s Cyclic ADC
This cyclic ADC, based on redundant-signed-digit (RSD) conversion, is optimized for power efficiency and high accuracy. It provides 16 bit resolution ...
279
7.0
Ultra-Low Power 6 - 13 Bit 0.5 -10 kS/s 10μW Analog Front End
The Analog-Frontend (AFE) IP consists of programmable current and voltage preamplifier followed by a Successive Approximation Register (SAR) architect...
280
7.0
Ultra-Low Power 6 - 13 Bit 1-10 kS/s 1.9 μW SAR ADC
The IP consists of a Successive Approximation Register (SAR) architecture ADC using charge-redistribution technique. The ADC IP is configurable regard...
281
7.0
Ultra-low power RF receiver / WakeUp receiver
The integrated ultra-low power receiver technology RFicient® was developed for ISM frequency bands and built in standard CMOS technology. The receiver...
282
7.0
USB 2.0 Full/Low-Speed Device Core
The FHG USB DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-speed USB 2.0 device functionality wi...
283
7.0
USB 2.0 Full/Low-Speed Embedded Host Controller
The FHG USB EHC is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-/low-speed USB 2.0 host functionality ...
284
7.0
USB 2.0 High/Full-Speed Device Core
The FHG USB2 DEV is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high-/full-speed USB 2.0 device functiona...
285
7.0
USB 2.0 High/Full/Low-Speed Embedded Host Controller
The FHG USB2 EHC is a scalable, high performance IP-module for usage in ASIC and FPGA designs to integrate high/full/low-speed USB 2.0 host functiona...
286
7.0
USB 2.0 OTG Full/Low-Speed Dual Role Core
The FHG USB OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate full-/low-speed USB 2.0 device and host ...
287
7.0
USB 2.0 OTG High/Full/Low-Speed Dual Role Core
The FHG USB2 OTGDRD is a scalable, high performance IP-Module for usage in ASIC- and FPGA-designs to integrate high/full/low-speed USB 2.0 device and ...
288
5.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPC-NS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
289
3.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-EW
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
290
2.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 16FF-NS
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
291
1.0
UFS 2.1 Device Controller compatible with MIPI M-PHY 3.1 and UniPro 1.6
Arasan Chip Systems is a leading SoC IP provider of a complete suite of JEDEC UFS compliant IP solutions, which consist of IP cores, verification IP, ...
292
1.0
UFS 2.1 Host Controller compatible with M-PHY 3.1 and UniPro 1.6
Arasan's Universal Flash Storage 2.1 (UFS 2.1) is a simple but high performance, serial interface primarily used in mobile systems, between host proce...
293
1.0
UFS 3.0 Host Controller compatible with M-PHY 4.0 and UniPro 1.8
Arasan's Universal Flash Storage 3.0 (UFS 3.0) is a simple but high performance, serial interface primarily used in mobile systems, between host proce...
294
1.0
Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto
The Gigabit Ethernet Media Access Controller with IEEE 1588 PTP IP core is compliant to the Ethernet/IEEE 802.3-2008 standard and has hardware based ...
295
0.0
10 Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto
The Arasan Gigabit Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3- 2008 standard. The Gigabit Ethernet IP provides a 10...
296
0.0
DAB Receiver Kit
The DAB Receiver Kit from Fraunhofer IIS is a fully validated DAB/DAB+/T-DMB solution for the automotive and consumer market. This innovative software...
297
0.0
Neo NPU - Scalable and Power-Efficient Neural Processing Units
Highly scalable performance for classic and generative on-device and edge AI solutions The Cadence Neo NPUs offer energy-efficient hardware-based AI ...
298
0.0
UFS 3.1 Host Controller compatible with M-PHY 4.1 and UniPro 1.8
The Arasan UFS Host -UniPro IP is a simple, high performance, serial interface used primarily in mobile systems between host processing and NVM mass s...
299
0.0
PHY for PCIe 5.0 and CXL for TSMC
Cadence 32G NRZ multi-protocol PHY The Cadence® 32/25Gbps Multi-Link and Multi-Protocol PHY IP for TSMC is a high-performance SerDes operating from 1...
300
0.0
PHY for PCIe 6.0 and CXL for Samsung
Most advanced PHY and Controller for HPC, AI/ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®) 6....