1351 3.0

802.11i CCMP/TKIP IP Core Implementation of the WLAN security standard (802.11i) requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and mess...

1352 3.0

802.15.3 CCM AES Core Implementation of the new WPAN security standard (802.15.3) requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and...

1353 3.0

1024 Point FFT The FFT1024 core implements 1024 or 512 point FFT in hardware. It can be dynamically configured to process one 1024 or two simultaneous 512 point FFT/...

1354 3.0

P1619/802.1ae (MACSec) GCM/XEX/XTS-AES Core General Description LAN security standard IEEE 802.1ae (MACSec) uses AES cipher in the GCM mode, while the disk/tape encryption standard IEEE P1619 us...

1355 3.0

32-512 Point Streaming FFT The FFT1-32-512/4 core implements 32, 64, 128, 256, and 512 point FFT and IFFT in hardware that runs at the clock frequency four times higher than the...

1356 3.0

32/64/128/256/512/1024/2048/4096 Point FFT Core The FFT4096 core the FFT and IFFT computations for N input samples, where N can be any power of 2 between 32 and 4096 (32, 64, 128,...…4096), in hardw...

1357 3.0

I2C Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus) The Digital Blocks DB-I2C-MS-AHB Controller IP Core interfaces a microprocessor via the AHB system Interconnect Fabric to an I2C Bus. The I2C is a t...

1358 3.0

I2C Master / Slave Controller w/FIFO (APB Bus) The Digital Blocks DB-I2C-MS-APB Controller IP Core interfaces a microprocessor via the APB system Interconnect Fabric to an I2C Bus. The I2C is a t...

1359 3.0

I2C Master Controller w/FIFO (APB Bus) The Digital Blocks DB-I2C-M-APB Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC, or other high performance microprocessor via the AMBA 2.0 AP...

1360 3.0

I2C Slave Controller - Low Power, Low Noise Config of User Registers The DB-I2C-S-SCL-CLK is an I2C Slave Controller IP Core focused on low power, low noise ASIC / ASSP designs requiring the configuration & control of r...

1361 3.0

I2C Slave Controller w/FIFO (APB or AHB or AHB-Lite or AXI-Lite Bus) The Digital Blocks DB-I2C-S-APB / DB-I2C-S-AHB / DB-I2C-S-AXI / DB-I2C-S-AVLN Controller IP Core interfaces an ARM, MIPS, PowerPC, ARC,NIOS II or othe...

1362 3.0

I2C Slave with AHB Master Bridge (I2C2AHB) The DB-I2C-S-AHB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & c...

1363 3.0

I2C Slave with APB Master Bridge (I2C2APB) The DB-I2C-S-APB-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & c...

1364 3.0

I2C Slave with AXI Master Bridge (I2C2AXI4) The DB-I2C-S-AXI-BRIDGE is an I2C Slave Controller IP Core focused on low VLSI footprint ASIC / ASSP designs not requiring internal configuration & c...

1365 3.0

64 POINT FFT The FFT0064 core implements 64 point FFT in hardware. FFT 64 works on blocks of 64 complex data samples....

1366 3.0

66/2112 Codec for Cyclic Code (2112,2080) The CEC1-66/2112 core implements the codec for the Forward Error Correction (FEC) cyclic code (2112,2080) used in the IEEE 802.3ap (10G Backplane Ethe...

1367 3.0

Kasumi Encryption Core The KSM1 core implements Kasumi encryption in compliance with the ETSI SAGE specification. It processes 64-bit blocks using 128-bit key. Basic core is...

1368 3.0

MBOA MAC AES Core Implementation of the new WPAN security standard for MBOA MAC requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption ...

1369 3.0

RC4 Keystream Generator The RC4 core implements the RC4 stream cipher in compliance with the ARC4 specification. It produces the keystream that consists of 8-bit words using ...

1370 3.0

Scalable RSA and Elliptic Curve Accelerator Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”. The operati...

1371 3.0

2D Graphics Hardware Accelerator (AXI4 Bus) The DB9200AXI4 2D Graphics Engine Verilog IP Core targets low VLSI footprint, high-performance hardware accelerated graphics applications. The DB92...

1372 3.0

HDCP 2.0 Encryption Suite HDCP Suite consists of hardware and software components implementing the HDCP 2.0 protocol. The hardware components are fully synchronous and availab...

1373 3.0

PDM to PCM Conversion, SMIC 65nmLL The AR36S01 is a soft macro low-power digital microphone interface modulator IP. The IP converts stereo/mono 1-bit pulse-density modulated (PDM) bit s...

1374 3.0

IEEE 802.11 WAPI Encryption Core Implementation of the new Chinese security standard (WAPI) requires running the SMS4 cipher in the WPI mode for encryption and message authentication....

1375 3.0

IEEE 802.15.4 (ZigBee) CCM* AES Cores IEEE 802.15.4 is the low-power wireless standard that is used by ZigBee Alliance as a base of its ZigBee™ specification. The security design of IEEE 8...

1376 3.0

IEEE 802.16e (WiMAX) AES Core Implementation of the new WLAN security standard (802.16e) requires the NIST standard AES cipher in CTR and CBC modes (a.k.a. CCM) for encryption and ...

1377 3.0

IEEE 802.1ae (MACsec) 100G Security Processor with Avalon-ST Interface Implementation of the new LAN security standard IEEE 802.1ae (MACsec) requires the NIST standard AES cipher in the GCM mode for encryption and message...

1378 3.0

IEEE 802.1ae (MACsec) Security Processor Implementation of the new LAN security standard IEEE 802.1ae (MACsec) requires the NIST standard AES cipher in the GCM mode for encryption and message...

1379 3.0

Generic CCM AES Core The CCM1 cores are tuned for mid-performance generic AES-CCM applications per NIST SP 800-38C. Specific protocol implementations are available in inte...

1380 3.0

Generic CCM AES Core with CMAC Option The CCM2 cores are tuned for mid-performance generic AES-CCM applications per NIST SP 800-38C. CCM2 core uses flow-trough design with dedicated input...

1381 3.0

SHA1, SHA2 Cryptographic Hash Cores The SHA cores provide implementation of cryptographic hashes SHA-1 (core SHA1), SHA-2 (cores SHA2-256 and SHA2-512). The cores utilize “flow-through”...

1382 3.0

UHS-II PHY for SD4/SD5 TSMC 12nm FF SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely ar...

1383 3.0

UHS-II PHY for SD4/SD5 TSMC 16nm FF SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely ar...

1384 3.0

High-Performance Lossless Compression Core Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. ...

1385 3.0

High-Performance Lossless Compression/Encryption Combo Core Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. ...

1386 3.0

MIPI D-PHY NEC 90nm Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...

1387 3.0

MIPI M-PHY Designed For GF 28nm ACS-AIP-MPHY-28HK MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A ...

1388 3.0

NIST AES Key Wrap/Unwrap Core AKW1 implements the NIST standard AES key wrap and unwrap. Core contains the base AES core AES1 and is available for immediate licensing. The design ...

1389 3.0

Elliptic Curve Point Multiply and Verify Core Elliptic Curve Cryptography (ECC) is a public-key cryptographic technology that uses the mathematics of so called “elliptic curves” and it is a part o...

1390 3.0

Ultra-Compact 3GPP Cipher Core The ZUC1 core implements ZUC stream cipher in compliance with the 3GPP Confidentiality and Integrity Algorithms 128-EEA3 & 128-EIA3 version 1.6. It pr...

1391 3.0

Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core The AES core implements Rijndael cipher encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit data bloc...

1392 3.0

Ultra-Compact Data Encryption Standard (DES/3DES) Core The DES1 ASIC/FPGA core is an implementation of the DES and triple DES encryption and decryption in compliance with the NIST Data Encryption Standard....

1393 3.0

eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-EW Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...

1394 3.0

SNOW 3G Encryption Core The SNOW3G1 core implements SNOW 3G stream cipher in compliance with the ETSI SAGE specification version 1.1. It produces the keystream that consists ...

1395 3.0

True Random and Pseudorandom Number Generator The true random generator core implements true random number generation. The core passes the American NIST Special Publication 800-22 and Diehard Rand...

1396 3.0

LRW-AES Core LRW3 implements the NIST standard AES cipher in the LRW mode for encryption and decryption. The LRW3 family of cores covers a wide range of area / thr...

1397 3.0

LRW-AES Core Implementation of the older drafts standard IEEE P1619 required the NIST standard AES cipher in the LRW mode for encryption (AES-LRW). Note that the n...

1398 3.0

LRW-AES Core Implementation of the new encrypted shared storage media standard IEEE P1619 with AES cipher in the LRW mode....

1399 3.0

Cryptographically Secure Pseudo Random number Generator IP Core The PRNG1 core implements a cryptographically secure pseudo-random number generator per NIST publication SP800-90. Basic core is small (6,500 gates)...

1400 3.0

Hs-Mode I2C Controller - 3.4 Mbps, Master / Slave w/FIFO The Digital Blocks DB-I2C-MS-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bu...