301 30.0

Process Detector (For DVFS and monitoring process variation), TSMC N7 An embedded process detector circuit which helps Integrated Circuit (IC) developers to address the problem of process variability on low-geometry CMOS...

302 30.0

TSMC CLN7FF 7nm Deskew PLL - 400MHz-2000MHz The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

303 30.0

TSMC CLN7FF 7nm General Purpose PLL - 400MHz-2000MHz The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

304 30.0

TSMC CLN7FF 7nm IoT PLL - 30MHz-1000MHz The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication ...

305 30.0

TSMC CLN7FF 7nm Multi Phase DLL - 800MHz-4000MHz The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....

306 30.0

Multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC) CoMira’s multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC) is fully configurable and pro...

307 28.0

Display Controller - LCD / OLED Panels (AXI Bus) The Digital Blocks DB9000AXI LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI Protocol Inter...

308 28.0

Display Controller - LCD / OLED Panels (AXI4 Bus) The Digital Blocks DB9000AXI4 LCD / OLED Display Controller IP Core interfaces a microprocessor and frame buffer memory via the AMBA AXI4 Protocol Int...

309 28.0

Slave side SPI/QPI controller 133MHZ This SPI/QPI PHY IP is fully compatible with Macronix NOR Flash SPI products. Max frequency hardware proven is 133MHz. Can be used for a variety of m...

310 28.0

LPDDR4x Secondary/Slave (memory side!) PHY This LPDDR4X PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR4X IP pr...

311 28.0

LPDDR4x/5 Secondary/Slave (memory side!) PHY This LPDDR4/4X/5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR4X/L...

312 28.0

LPDDR5 Secondary/Slave (memory side!) PHY This LPDDR5 PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR5 IP prov...

313 28.0

LPDDR5X Secondary/Slave (memory side!) PHY This LPDDR5X PHY is a memory-side interface IP normally found implemented within commodity DRAM products. Green Mountain Semiconductor's LPDDR5X IP pr...

314 25.0

I3C Advanced Controller, V1.1 I3C is a new a standard from the MIPI Alliance that unifies and extends the legacy interfaces of I2C and SPI and adds new powerful features to sup...

315 25.0

I3C Advanced Controller, V1.1 Lite The I3C Advanced Controller Lite is a highly configurable I3C controller that can be used in microcontroller-based environments to provide I3C con...

316 25.0

I3C Advanced Target, V 1.1 Lite The I3C Advanced Target Lite is a highly configurable I3C Target that can be used in microcontroller based environments to provide I3C connectivit...

317 25.0

I3C Advanced Target, V1.1 The I3C Advanced Target is a highly configurable I3C Target that can be used in microcontroller based environments to provide I3C connectivity to ...

318 25.0

I3C Autonomous Target, V1.1 The I3C Autonomous Target is intended for simple, data acquisition types of applications where a microprocessor is not needed to process the data....

319 25.0

WAVE-P, Advanced Professional Video, APV New! Advanced Professional Video (APV) codec is a new codec for prosumers ​ who do not want to compromise on quality while enjoying the convenience of ​ ...

320 25.0

HBM2E PHY V2 (Hard 1) in TSMC (N7, N6, N5) The Synopsys HBM2/HBM2E PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), graphics, and networking A...

321 25.0

HBM2E PHY V2 in TSMC (N7, N6, N5) The Synopsys HBM2/HBM2E PHY is a complete physical layer IP interface (PHY) solution for high-performance computing (HPC), graphics, and networking A...

322 25.0

LDO Voltage Regulator 250 mA, TSMC N3P The LDO IP is a 1.2V low-quiescent-current adjustable output voltage Low-Drop-Out (LDO) Linear Regulator implemented in the TSMC 3nm N3P CMOS process ...

323 25.0

LDO Voltage Regulator Adjustable 0.45 V to 0.9 V Output, 30 mA The LDO IP is a 1.2V low-quiescent-current adjustable output voltage Low-Drop-Out (LDO) Linear Regulator implemented in the TSMC 3nm N3P CMOS process ...

324 25.0

1G/10G TCP/IP Hardware Stack The TCPIP-1G/10G core implements a complete TCP/IP Hardware Protocol Stack. More capable than many offloading engines, it allows systems to connect to...

325 25.0

LINFlexD Controller The LINFlexD Controller is a serial communication interface designed for Local Interconnect Network (LIN) applications. The LINFlexD manages a high nu...

326 25.0

MIPI C-PHY v1.1 Combination MIPI CPHY-DPHY Analog Interface The MIPI C-PHY V1.0 improves throughput over a bandwidth limited channel, allowing more data without in...

327 25.0

MIPI C-PHY V1.1 TSMC 28nm HPC+ Combination MIPI CPHY-DPHY Analog Interface The MIPI C-PHY V1.1 improves throughput over a bandwidth limited channel, allowing more data without in...

328 25.0

MIPI C-PHY-D-PHY Combo PHY IP on TSMC 28nm HPC+ Combination MIPI CPHY-DPHY Analog Interface The MIPI C-PHY V1.0 improves throughput over a bandwidth limited channel, allowing more data without in...

329 25.0

MIPI D-PHY Tx v1.1 ONLY @1.5ghz Ultra Low Power & Low Area for IoT & Wearables Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on TSMC 22nm process technology for SoC designs. Arasan’s D-PHY IP is a...

330 25.0

MIPI D-PHY V1.2@2.5GHz TSMC28nm HPC+ Arasan has the industry’s broadest portfolio of foundry and process technology support for MIPI D-PHY in the industry. The MIPI D-PHY analog IP is ava...

331 25.0

FlexCAN Controller The FlexCAN controller is a highly configurable, synthesizable core implementing the CAN protocol (ISO 11898-1), CAN with Flexible Data rate (CAN FD),...

332 25.0

FlexRay Controller The FlexRay Controller fully complies with FlexRay Communication System Protocol Specification, Version 2.1, Revision A. It implements the specificati...

333 25.0

Ultra-Fast Baseline and Extended JPEG Decoder Core This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements ...

334 25.0

ONFI 5.0 Controller Arasan Chip System’s NAND flash controller IP provides easy, reliable access to an off-chip NAND flash. It supports all modes of the Open NAND Flash I...

335 25.0

ONFI 5.0 PHY Open NAND Flash Interface (ONFI) for NAND Flash Memory chips is an open standard. Arasan’s ONFI 5.0 PHY IP is designed to connect seamlessly with thei...

336 25.0

LPDDR5X/5/4X/4 Memory Controller IP OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

337 25.0

LPDDR5X/5/4X/4 PHY for 16nm The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...

338 25.0

LPDDR5X/5/4X/4 PHY IP for 12nm The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...

339 25.0

Process Detector (For DVFS and monitoring process variation) An embedded process detector circuit which helps Integrated Circuit (IC) developers to address the problem of process variability on low-geometry CMOS...

340 25.0

Process Detector (For DVFS and monitoring process variation) An embedded process detector circuit which helps Integrated Circuit (IC) developers to address the problem of process variability on low-geometry CMOS...

341 25.0

Process Detector (For DVFS and monitoring process variation) An embedded process detector circuit which helps Integrated Circuit (IC) developers to address the problem of process variability on low-geometry CMOS...

342 25.0

Process Detector (For DVFS and monitoring process variation), TSMC 12FFC An embedded process detector circuit which helps Integrated Circuit (IC) developers to address the problem of process variability on low-geometry CMOS...

343 25.0

TSN Ethernet Endpoint Controller The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking ...

344 25.0

TSN Ethernet Switch The TSN-SW implements a highly flexible, low-latency TSN Ethernet switch. It supports Ethernet bridging according to the IEEE 802.1Q-2018 standard and...

345 25.0

MultiCAN Controller Since its introduction in the mid-1980s, the Controller Area Network (CAN) has become a standard network protocol for automotive applications. Cars ma...

346 20.0

1.8V/3.3V I2C 5V Failsafe Failtolerant Automotive Grade 1 in GF (12nm) Synopsys Inter-Integrated Circuit (I2C) I/O library is used for two wire interfaces to connect low-speed devices like EEPROM, A/D, and D/A converters ...

347 20.0

1.8V/3.3V I2C 5V Failsafe Failtolerant Automotive Grade 1 in GF (22nm) Synopsys Inter-Integrated Circuit (I2C) I/O library is used for two wire interfaces to connect low-speed devices like EEPROM, A/D, and D/A converters ...

348 20.0

1.8V/3.3V I2C in GF (12nm) Synopsys Inter-Integrated Circuit (I2C) I/O library is used for two wire interfaces to connect low-speed devices like EEPROM, A/D, and D/A converters ...

349 20.0

10 Gigabit Ethernet MAC with IEEE 1588 PTP Support and AVB for Auto The 10 Gigabit Ethernet Media Access Controller with IEEE 1588 PTP IP core is compliant to the Ethernet/IEEE 802.3-2008 standard and has hardware bas...

350 20.0

I3C Dual Controller The Arasan I3C Secondary Controller IP Core implements Active controller functionality as defined by the MIPI Alliance’s I3C Specification and Seconda...