451 20.0

LPDDR4X multiPHY in Samsung (14nm, 11nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

452 20.0

LPDDR4X multiPHY in TSMC (16nm, 12nm,N7, N6) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

453 20.0

LPDDR4X multiPHY Plus in GF (12nm) The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...

454 20.0

LPDDR4x/4 PHY IP for 22nm OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

455 20.0

LPDDR5/4/4X PHY in GF (12nm) The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in-package a...

456 20.0

LPDDR5/4/4X PHY in TSMC (16nm, 12nm, N7, N6, N5) The Synopsys LPDDR5/4/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in-package a...

457 20.0

LPDDR5X/5/4X PHY in Samsung (SF4X, SF2) The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...

458 20.0

LPDDR5X/5/4X/4 combo PHY at 12nm The LPDDR5X/5/4X/4 combo PHY IP features a state-of-art mixed-signal architecture that addresses the challenges of DRAM integration in high-performan...

459 20.0

GPIO 1.8V Automotive Grade 1 in GF (22nm) Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

460 20.0

GPIO 1.8V FS Automotive Grade 1 in GF (22nm) Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

461 20.0

Pre-verified Interface IP Subsystems reduce design risk and accelerate time-to-market Customers are increasingly utilizing third-party standards-based IP in their designs, but face several challenges. With more IP and more complex inter...

462 20.0

Front-end voice processing software package providing enhanced speech intelligibility for voice-enabled devices ClearVox is a software suite of advanced voice input processing algorithms aimed to enhance voice clarity in any voice-enabled device. Voice has be...

463 20.0

USB 3.0 PHY in TSMC (65nm, 55nm, 40nm, 28nm) The Synopsys USB-C™ 3.0 and USB 3.0 femtoPHY IP provide designers with a complete physical (PHY) layer IP solution for low-power mobile and consumer a...

464 20.0

DSC Decoder Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data compression and has b...

465 20.0

DSC Encoder Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data compression and has b...

466 20.0

TSMC 4nm (N4P) 1.2V/1.8V Basekit Libraries Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality, foundation IP, including memory compilers, logic librarie...

467 20.0

TSMC 4nm (N4P) 1.2V/1.8V Basekit Libraries, multiple metalstacks Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality, foundation IP, including memory compilers, logic librarie...

468 20.0

TSMC 4nm (N4P) 1.2V/1.8V I3C Libraries Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

469 20.0

TSMC 4nm (N4P) 1.2V/1.8V/2.5V Failsafe GPIO Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

470 20.0

TSMC 4nm (N4P) 1.8V SD/eMMC IO Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

471 20.0

TSMC 4nm (N4P) 1.8V SD/eMMC PHY Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

472 20.0

TSMC 4nm (N4P) 2.5V Basekit Libraries Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality, foundation IP, including memory compilers, logic librarie...

473 20.0

TSMC 4nm (N4P) 2.5V Basekit Libraries, multiple metalstacks Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality, foundation IP, including memory compilers, logic librarie...

474 20.0

TSMC 5nm (N5) 1.2V/1.8V Basekit Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

475 20.0

TSMC 5nm (N5) 1.2V/1.8V Failsafe GPIO Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

476 20.0

TSMC 5nm (N5) 1.2V/1.8V Failsafe GPIO Libraries, multiple metalstacks Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

477 20.0

TSMC 5nm (N5) 1.2V/1.8V I3C Libraries Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

478 20.0

TSMC 5nm (N5) 1.2V/1.8V/2.5V Failsafe GPIO Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

479 20.0

TSMC 5nm (N5) 1.2V/1.8V/2.5V GPIO Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

480 20.0

TSMC 5nm (N5) 1.2V/1.8V/2.5V GPIO Libraries, multiple metalstacks Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

481 20.0

TSMC 5nm (N5) 1.8V SD/eMMC IO Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

482 20.0

TSMC 5nm (N5) 1.8V SD/eMMC PHY Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

483 20.0

TSMC 5nm (N5) 2.5V Basekit Libraries Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

484 20.0

TSMC 5nm (N5)1.8V SD/eMMC PHY, multiple metalstacks Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

485 20.0

TSMC 6nm (6FF) 3.3V GPIO Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

486 20.0

TSMC 6nm (6FF) 3.3V SMBUS (I2C) IO Synopsys Inter-Integrated Circuit (I2C) I/O library is used for two wire interfaces to connect low-speed devices like EEPROM, A/D, and D/A converters ...

487 20.0

TSMC 6nm (N6) 3.3V Basekit Libraries Synopsys provides system-on-chip (SoC) designers with an extensive offering of high-quality, foundation IP, including memory compilers, logic librarie...

488 20.0

TSMC 7nm (7FF) 1.8V LVDS Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

489 20.0

TSMC 7nm (7FF) 3.3V GPIO Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

490 20.0

TSN Ethernet Switched Endpoint Controller The TSN-SE implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking ...

491 20.0

xSPI Flash Memory Controller The xSPI-MC core is a versatile serial flash memory controller, which allows a system to easily detect and access the attached flash device or directl...

492 20.0

Multipurpose Security Protocol Accelerator Complex system-on-chip (SoC) requirements can include security at the MAC layer, VPN layer, and application layer. The SynopsysSecurity Protocol Accel...

493 20.0

eUSB 2.0 PHY IP Arasan Chip Systems, the leading provider of IP for Mobile and Automobile SOC’s, presents its latest eUSB2 IP. Embedded USB2 (eUSB2) is a new generati...

494 20.0

Automotive-grade MIPI CSI-2 host/device controllers for high-speed serial interface between image processor and camera sensors Synopsys MIPI® IP solution enables low-power and high-performance interface between system-on-chips (SoCs), application processors, baseband processor...

495 20.0

NVM FTP Trim in SMIC (180nm, 110nm) Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD proc...

496 20.0

NVM FTP Trim in TowerJazz (180nm) Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD proc...

497 20.0

NVM FTP Trim in TSMC (180nm, 152nm, 90nm) Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD proc...

498 20.0

NVM MTP in GF (180nm, 55nm) Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD proc...

499 20.0

NVM MTP in Samsung (130nm) Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD proc...

500 20.0

NVM MTP in Silterra (180nm) Synopsys Non-Volatile Memory (NVM) IP provides reprogrammable NVM supporting up to 1 million bits (1Mbit) configurations in standard CMOS and BCD proc...