Design & Reuse
Catalog of SIP Cores
System on Chip design resources
8768 IP
3501
0.0
Low Power 5V->2.4V Low noise LDO IP core
A 5V -> 2.4V low power LDO (Low Drop-Out) is a type of voltage regulator designed to provide a stable output voltage of 2.4 volts from a 5-volt input ...
3502
0.0
Low Power 5V->3.0V Cap-less LDO IP Core
A 5V -> 3.3V low power LDO (Low Drop-Out) is a type of voltage regulator designed to provide a stable output voltage of 3.3 volts from a 5 volt input ...
3503
0.0
Low power 8bit 300Ksps R2R Compact area High performance Silicon Proven DAC IP Core
The 8-bit 300 Ksps DAC IP Core employs a high-performance R2R architecture and provides an optional differential current output or differential voltag...
3504
0.0
Low Power High Speed 1.2GHz Frac-N PLL IP Core
A programmable on-the-fly Fractional-N PLL at 1.2GHz is required to lock to an incoming clock source and produce an output clock available at 40nm....
3505
0.0
Low Power High Speed 1GHz Frac-N PLL IP Core
An ultra-low-power programmable fractional-N at 1GHz phase-locked loop (PLL) for frequency synthesis available at 28nm....
3506
0.0
Low power24bitAudio Compact area Silicon Proven DAC IP Core
The 24bit Audio DAC IP Core employs a high-performance architecture and provides an optional differential current output or differential voltage outpu...
3507
0.0
Low PowerHigh Speed 1.6GHz Frac-N PLL IP Core
A programmable on-the-fly Fractional-N PLL at 1.6GHz is required to lock to an incoming clock source and produce an output clock available at 110nm...
3508
0.0
BoW Verification IP
Truechip's BoW Verification IP provides an effective & efficient way to verify the BoW components of an IP or SoC. Truechip's VIP is fully compliant w...
3509
0.0
Low-power, High Performance AI Accelerator
NovuTensor™ IP cores provide highly configurable AI acceleration capabilities with industry-leading performance efficiency. This patented, domain-spec...
3510
0.0
Power on Reset IP, Input: 1.2V, UMC 0.13um HS/FSG process
Vrr=0.8V Vfr=0.65V, VCC=1.2V, Ivcc=12.7uA, HS process with B-type IO., Power On Reset, UMC 0.13um HS/FSG Logic process....
3511
0.0
Power-On-Reset IP
INNOSILICON™ Power-On-Reset (POR) IP provides reliable reset functions for a variety of applications. It is powered by an analog supply and monitors b...
3512
0.0
IP Platform for Bluetooth 5.2
The LP1-200 IP Platform is built around the Bluetooth 5 connectivity standard. It consists of a Bluetooth 5.2 Low Energy and BR-EDR controllers, an o...
3513
0.0
IP Platform for Low Power IoT
With expertise in signal processing, wireless communication security and AI, we provide our customer with highly secure solutions for IoT devices at ...
3514
0.0
IP platform with integrated Functional Safety Monitor
This IP platform provides a framework to support a customer s own IP, which results in a faster time to market and lower risk. The SFA250A is aimed at...
3515
0.0
IP Suite for Premium Mobile Experiences
Over the last five years, we’ve seen CPU performance on smartphones increase an average of 20+ percent every year without compromising battery li...
3516
0.0
VP8 Decoder IP
VP8 Decoder core is compliant with VP-8 standard specification. Through its compatibility, it provides a simple interface to a wide range of low-cost ...
3517
0.0
VP8 Encoder IP
VP8 Encoder core is compliant with VP-8 standard specification. Through its compatibility, it provides a simple interface to a wide range of low-cost ...
3518
0.0
Spacewire Verification IP
Truechip's SpaceWire Verification IP provides an effective & efficient way to verify the components interfacing with SpaceWire interface of an ASIC/FP...
3519
0.0
APB Multilayer Interconnect IP
SmartDV’s APB (Advanced Peripheral Bus) Multilayer Interconnect IP enables efficient communication between multiple APB masters and slaves, streamlini...
3520
0.0
APB to AHB Bridge IP
SmartDV’s APB to AHB Bridge IP enables seamless communication between low-bandwidth peripheral devices on the APB (Advanced Peripheral Bus) and high-p...
3521
0.0
APB to AXI Bridge IP
SmartDV’s APB to AXI Bridge IP enables seamless protocol conversion between the low-bandwidth APB (Advanced Peripheral Bus) and the high-performance A...
3522
0.0
LPC Device IP
SmartDV’s LPC (Low Pin Count) Device IP is a silicon-proven solution designed to enable reliable, low-bandwidth communication between embedded control...
3523
0.0
LPC Host IP
SmartDV’s LPC (Low Pin Count) Host IP is a silicon-proven solution that enables efficient communication with LPC-compliant peripheral devices. Designe...
3524
0.0
FPD-Link (Flat Panel Display Link) Verification IP
FPD-Link Verification IP is fully compliant with Standard FPD Link I, II and III. It includes an extensive test suite covering most of the possible sc...
3525
0.0
LPDDR Controller IP
LPDDR is full-featured, easy-to-use, synthesizable design, compatible with JESD209A-1 and JESD209B specification. Through its LPDDR compatibility, it ...
3526
0.0
LPDDR2 Controller IP
LPDDR2 interface provides full support for the LPDDR2 interface, compatible with JESD209-2E and JESD209-2F specification. Through its LPDDR2 compatibi...
3527
0.0
LPDDR3 Controller IP
SmartDV’s LPDDR3 Controller IP offers a high-performance and low-latency solution for integrating LPDDR3 memory interfaces into SoCs and FPGA-based sy...
3528
0.0
LPDDR3 Verification IP
Truechip's LPDDR3 Verification IP provides an effective & efficient way to verify the components interfacing with LPDDR3 interface of an ASIC/FPGA or ...
3529
0.0
LPDDR4 Controller IP
SmartDV’s LPDDR4 Controller IP is a high-performance solution designed to enable fast, power-efficient memory access in mobile, automotive, and high-p...
3530
0.0
LPDDR4 Verification IP
Truechip's LPDDR4 Verification IP provides an effective & efficient way to verify the components interfacing with LPDDR4 interface of an ASIC/FPGA or ...
3531
0.0
LPDDR4/ DDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
The LPDDR4/ DDR4/ DDR3L Combo PHY IP offers low latency and supports throughput of up to 1866Mbps. The PHY IP is silicon validated in the TSMC 28HPC+ ...
3532
0.0
LPDDR5 Controller IP
SmartDV’s LPDDR5 Controller IP delivers high-bandwidth, low-latency memory access optimized for next-generation mobile, automotive, and AI/ML applicat...
3533
0.0
LPDDR5 IP - High performance and low power
With sophisticated architecture and advanced technology, KNiulink provide LPDDR5 with high performance and low power. In advanced process nodes, KNiu...
3534
0.0
LPDDR5 Verification IP
Truechip's LPDDR5 Verification IP provides an effective & efficient way to verify the components interfacing with LPDDR5 interface of an ASIC/FPGA or ...
3535
0.0
LPDDR5X Controller IP
LPDDR5X is full-featured, easy-to-use, synthesizable design, compatible with LPDDR5X draft JEDEC specification and DFI-version 5.0 specification Compl...
3536
0.0
SPDIF (IEC60958) Verification IP
SPDIF Verification IP provides an smart way to verify the SPDIF component of a SOC or a ASIC. The SmartDV s SPDIF Verification IP is fully compliant w...
3537
0.0
SPDIF IP
The SmartDV SPDIF IIP Core is full-featured, easy-to-use, synthesizable design that is easily integrated into any SOC or FPGA development. The SPDIF I...
3538
0.0
Specialty SSTL IO IP, UMC 0.18um G2 process
UMC 0.18um GII Logic process true 2.5V SSTL2 IO cells....
3539
0.0
MPEG2 Decoder IP
MPEG2 Decoder core is compliant with MPEG-2 standard specification. Through its compatibility, it provides a simple interface to a wide range of low-c...
3540
0.0
MPEG2 Encoder IP
MPEG2 Encoder core is compliant with MPEG-2 standard specification. Through its compatibility, it provides a simple interface to a wide range of low-c...
3541
0.0
MPEG4 Decoder IP
MPEG4 Decoder core is compliant with MPEG-4 standard specification. Through its compatibility, it provides a simple interface to a wide range of low-c...
3542
0.0
MPEG4 Encoder IP
MPEG4 Encoder core is compliant with MPEG-4 standard specification. Through its compatibility, it provides a simple interface to a wide range of low-c...
3543
0.0
Open Core Protocol (OCP) Verification IP
OCP : Asiczen Technologies has its IP verification for OCP (Open core protocol). OCP is one of the system Bus protocol verification IP. The system bus...
3544
0.0
Open LVDS Display Interface (OpenLDI) Verification IP
Open LVDS Display Interface(OpenLDI) specification was developed through the cooperation of companies in the semiconductor, display, computer system, ...
3545
0.0
Open Nand Flash Interface (ONFI) Verification IP
ONFI (Open Nand Flash Interface) provides an smart way to verify the ONFI host controller or ONFI Flash memory model of a SOC or a ASIC. The SmartDV s...
3546
0.0
SphinX - AES-XTS encryption/decryption IP
SphinX is designed to accommodate the speed, latency and throughput requirements of computer systems main memory. The IP implements the standard (NIST...
3547
0.0
XPHY Low power Chip to Chip SerDes IP, Silicon Proven in ST 28FDSOI
These IPs are targeted at applications requiring high speed, high bandwidth, low-power consumption, and low-latency interfaces....
3548
0.0
SPI Master IP
SPI Master is full-featured, easy-to-use, synthesizable design, compatible with SPI Block Guide 4.01 Complient. Through its SPI Master compatibility, ...
3549
0.0
SPI Slave IP
SPI Slave interface provides full support for the both three and four wire SPI synchronous serial interface, compatible with SPI specification SPI Blo...
3550
0.0
SPI Slave To AHB Bridge IP
SPI Slave To AHB Bridge interface provides full support for the two-wire SPI synchronous serial interface, compatible with SPI version Block Guide 4.0...