Analog Bits Inc. IP Cores

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2301

1.0

TSMC CL015LV 150nm Clock Generator PLL - 70MHz-350MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2302

1.0

TSMC CL015LV 150nm DDR DLL - 120MHz-600MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2303

1.0

TSMC CL015LV 150nm DDR DLL - 57MHz-285MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2304

1.0

TSMC CL015LV 150nm DDR DLL - 76MHz-380MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2305

1.0

TSMC CL015LV 150nm Deskew PLL - 140MHz-700MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2306

1.0

TSMC CL015LV 150nm Deskew PLL - 280MHz-1400MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2307

1.0

TSMC CL015LV 150nm Deskew PLL - 70MHz-350MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2308

1.0

TSMC CL015LV 150nm Spread Spectrum PLL - 140MHz-700MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2309

1.0

TSMC CL015LV 150nm Spread Spectrum PLL - 280MHz-1400MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2310

1.0

TSMC CL015LV 150nm Spread Spectrum PLL - 70MHz-350MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2311

1.0

TSMC CL018E 180nm Clock Generator PLL - 130MHz-650MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2312

1.0

TSMC CL018E 180nm Clock Generator PLL - 260MHz-1300MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2313

1.0

TSMC CL018E 180nm Clock Generator PLL - 65MHz-325MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2314

1.0

TSMC CL018E 180nm DDR DLL - 120MHz-600MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2315

1.0

TSMC CL018E 180nm DDR DLL - 57MHz-285MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2316

1.0

TSMC CL018E 180nm DDR DLL - 76MHz-380MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2317

1.0

TSMC CL018E 180nm Deskew PLL - 130MHz-650MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2318

1.0

TSMC CL018E 180nm Deskew PLL - 260MHz-1300MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2319

1.0

TSMC CL018E 180nm Deskew PLL - 65MHz-325MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2320

1.0

TSMC CL018E 180nm Spread Spectrum PLL - 130MHz-650MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2321

1.0

TSMC CL018E 180nm Spread Spectrum PLL - 260MHz-1300MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2322

1.0

TSMC CL018E 180nm Spread Spectrum PLL - 65MHz-325MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2323

1.0

TSMC CL018G 180nm Clock Generator PLL - 110MHz-550MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2324

1.0

TSMC CL018G 180nm Clock Generator PLL - 220MHz-1100MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2325

1.0

TSMC CL018G 180nm Clock Generator PLL - 55MHz-275MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2326

1.0

TSMC CL018G 180nm DDR DLL - 42MHz-210MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2327

1.0

TSMC CL018G 180nm DDR DLL - 56MHz-280MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2328

1.0

TSMC CL018G 180nm DDR DLL - 88MHz-440MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2329

1.0

TSMC CL018G 180nm Deskew PLL - 110MHz-550MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2330

1.0

TSMC CL018G 180nm Deskew PLL - 220MHz-1100MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2331

1.0

TSMC CL018G 180nm Deskew PLL - 55MHz-275MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2332

1.0

TSMC CL018G 180nm Spread Spectrum PLL - 110MHz-550MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2333

1.0

TSMC CL018G 180nm Spread Spectrum PLL - 220MHz-1100MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2334

1.0

TSMC CL018G 180nm Spread Spectrum PLL - 55MHz-275MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2335

1.0

TSMC CL018LP 180nm Clock Generator PLL - 180MHz-900MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2336

1.0

TSMC CL018LP 180nm Clock Generator PLL - 45MHz-225MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2337

1.0

TSMC CL018LP 180nm Clock Generator PLL - 90MHz-450MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2338

1.0

TSMC CL018LP 180nm DDR DLL - 30MHz-150MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2339

1.0

TSMC CL018LP 180nm DDR DLL - 40MHz-200MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2340

1.0

TSMC CL018LP 180nm DDR DLL - 63MHz-315MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2341

1.0

TSMC CL018LP 180nm Deskew PLL - 180MHz-900MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2342

1.0

TSMC CL018LP 180nm Deskew PLL - 45MHz-225MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2343

1.0

TSMC CL018LP 180nm Deskew PLL - 90MHz-450MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2344

1.0

TSMC CL018LP 180nm Spread Spectrum PLL - 180MHz-900MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2345

1.0

TSMC CL018LP 180nm Spread Spectrum PLL - 45MHz-225MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2346

1.0

TSMC CL018LP 180nm Spread Spectrum PLL - 90MHz-450MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2347

1.0

TSMC CL018LV 180nm Clock Generator PLL - 118MHz-590MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2348

1.0

TSMC CL018LV 180nm Clock Generator PLL - 236MHz-1180MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2349

1.0

TSMC CL018LV 180nm Clock Generator PLL - 59MHz-295MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2350

1.0

TSMC CL018LV 180nm DDR DLL - 101MHz-505MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

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