Design & Reuse
Catalog of SIP Cores
System on Chip design resources
5620 IP
701
100.0
PCIe 7.0 PHY IP supporting the latest features of the evolving PCIe 7.0 specification to enable 128 GT/s and up to x16 lane configurations
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...
702
100.0
UCIe PHY & D2D Adapter
Neuron IP’s UCIe PHY & D2D Adapter IP portfolio includes 32Gbps UCIe-Advanced (UCIe-A) & Standard (UCIe-S) cores as per the latest UCIe v1.1 specifica...
703
100.0
UCIe-A PHY for Advanced Package (x64) in TSMC (N7, N6, N5, N3)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
704
100.0
UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
705
100.0
UCIe-S PHY for Standard Package (x16) in TSMC (N7, N6, N4P, N5, N3)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
706
100.0
Adaptive Clock Generation Module for DVFS and Droop Response
The Movellus™ Aeonic Generate AWM3 high-performance clock generation IP product is part of the Aeonic digital IP product family. Designed for Droop Mi...
707
100.0
HDCP 2.3 Embedded Security Modules on DisplayPort/USB Type-C
The Synopsys Embedded Security Modules (ESMs) for High- Bandwidth Digital Content Protection 2.3 (HDCP 2.3) are complete solutions that provide design...
708
100.0
Aeonic Generate Digital PLL for multi-instance, core logic clocking
The Movellus™ high-performance Aeonic Generate Clock Generation Module (CGM) is a high-quality digital PLL that enables distributed clocking for per-c...
709
100.0
Ceva-Waves Bluetooth 6.0 Low Energy Baseband Controller / Link Layer, software and profiles
Ceva-Waves Bluetooth Low Energy IP is a comprehensive and flexible solution for integration into SoCs/ASSPs. It has been qualified for Bluetooth Core ...
710
100.0
1G-25G MACsec Security Module
Data security between Ethernet-connected devices is expanding due to multiple factors: exponential growth of data containing sensitive and private inf...
711
100.0
The Synopsys 1.6T Ethernet MAC IP is based on IEEE 802.3-2018 spec for 400Gbps, 800Gbps & 1.6Tbps Ethernet applications
The Synopsys 1.6T Ethernet MAC IP implements the functions required by the IEEE 802.3-2018 specification to communicate over Ethernet providing a simp...
712
100.0
Embedded Security Modules for HDCP 2.3 on HDMI IP
The Synopsys Embedded Security Modules (ESMs) for High- Bandwidth Digital Content Protection 2.3 (HDCP 2.3) are complete solutions that provide design...
713
100.0
Universal Chiplet Interconnect Express (UCIe) Controller
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...
714
100.0
Inline Memory Encryption (IME) Security Module for DDR/LPDDR
As our connected world expands, the technological advances in high-performance computing (HPC) are reshaping system-on-chip (SoC) designs to address t...
715
100.0
Integrated Droop Response System
Industry 1st Integrated Turnkey Solution for Droop and DVFS Response Enabling Silicon Monitoring and Health Analytics with Precise Run-Time Droop R...
716
100.0
ApSRAM Controller
Mobiveil’s ApSRAM Controller is a highly flexible, low-latency, and low-power IP core designed to serve as a high-performance replacement for traditio...
717
100.0
NPU IP family for generative and classic AI with highest power efficiency, scalable and future proof
NeuPro-M™ redefines high-performance AI (Artificial Intelligence) processing for smart edge devices and edge compute with heterogeneous coprocessing, ...
718
100.0
NPU IP for Embedded AI
Ceva-NeuPro-Nano is a highly efficient, self-sufficient Edge NPU designed for TinyML applications​. It delivers the optimal balance of ultra-low power...
719
100.0
USB4 Controller & Router IP
The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...
720
100.0
USB4 PHY in Samsung (SF4X)
The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...
721
100.0
USB4 PHY in TSMC (N7, N6, N5, N4P, N3E, N3P)
The Synopsys USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF). The USB4 IP offering includes device router,...
722
100.0
TSMC CLN4P 4nm DDR5 PHY - 6400Mbps
The TCI DDR PHY is a high-performance, scalable system using a radically new architecture that continuously and automatically adjusts each pin individ...
723
100.0
TSMC CLN7FF 7nm Clock Generator PLL - 800MHz-4000MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
724
100.0
TSMC CLN7FF 7nm DDR DLL - 250MHz-1250MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
725
100.0
TSMC CLN7FF 7nm Spread Spectrum PLL - 700MHz-3500MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
726
100.0
TSMC CLN7FF 7nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, featu...
727
100.0
TSMC CLN7FFLVT 7nm DDR DLL - 360MHz-1800MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
728
100.0
TSMC CLN7FFLVT 7nm Deskew PLL - 300MHz-1500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
729
100.0
TSMC CLN7FFLVT 7nm Multi Phase DLL - 1200MHz-6000MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
730
100.0
RT-120 Compact Root of Trust for IoT and IIoT, sensors and gateways
Rambus Hardware Root of Trust RT-120 is a state-machine-based hardware security core offering security by design. It protects against a wide range of ...
731
100.0
Multiport/Multiprotocol HDCP 2.3 Embedded Security Modules
The Synopsys Embedded Security Modules (ESMs) for High- Bandwidth Digital Content Protection 2.3 (HDCP 2.3) are complete solutions that provide design...
732
100.0
CXL 2.0 Integrity and Data Encryption Security Module
The Compute Express Link (CXL) interface protocol enables low-latency data communication between system-on-chip (SoC) and general-purpose accelerators...
733
100.0
Synopsys 100G/200G/400G/800G Ethernet MAC IP
The Synopsys 100G/200G/400G/800G Ethernet MAC IP implements the full MAC layer and reconciliation sublayer compliant with the IEEE 802.3 specification...
734
99.0
TSMC CLN20SOC 20nm Clock Generator PLL - 700MHz-3500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
735
99.0
TSMC CLN20SOC 20nm Deskew PLL - 700MHz-3500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
736
95.0
MACsec Engine 100-400Gbps Multi-Channel
As part of Rambus' award-winning silicon Intellectual Property (IP) product portfolio, the EIP-164 is a high-performance MACsec frame processing engi...
737
95.0
MACsec Engine 800G Multi-Channel
As part of Rambus' award-winning silicon Intellectual Property (IP) product portfolio, the MACsec-164 is a high-performance MACsec frame processing e...
738
90.0
12-bit, 9.2 GSPS Analog-to-Digital Converter (ADC) GlobalFoundries 22nm
The A12B9G is a low-power, high-speed analog to digital converter (ADC) intellectual property (IP) design block. It is a time-interleaved successive a...
739
90.0
Ceva-Waves Bluetooth 5.4 Low Energy Baseband Controller / Link Layer, software and profiles
Ceva-Waves Bluetooth 5.4 Low Energy IP is a comprehensive and flexible solution for integration into SoCs/ASSPs. The Ceva-Waves BLE hardware baseb...
740
90.0
GF L28SLP 28nm IoT PLL - 30MHz-550MHz
The IoT PLL is designed for very low power, sipping only 45uW at 30MHz and running from core power. It has a wide frequency range with multiplication ...
741
90.0
TSMC CLN16FF+LL 16nm Ultra PLL - 15MHz-3000MHz
The Ultra PLL is designed with a state-of-the-art architecture using high-speed digital and analog circuits that offers exceptional performance, featu...
742
90.0
TSMC CLN20SOC 20nm Spread Spectrum PLL - 306MHz-1530MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
743
80.0
WAVE6331, AV1, H.265, HEVC, H.264, AVC, VP9 video codec IP for 4K and 8K New!
WAVE6331 is a 4K/8K multi-standard video codec HW IP that supports AV1, HEVC/H.265, AVC/H.264, and VP9 video codec standard. It provides 8K30fps/4K120...
744
80.0
LDPC Encoder/Decoder (LDPC)
Mobiveil’s LDPC Encoder / Decoder* is a flash reliability solution delivering industry-leading flash endurance and retention through advanced LDPC err...
745
80.0
CFrame60, lossy, lossless FBC compression, decompression IP
The Chips&Media’s CFrame60 is a Lossless & Lossy Frame Compression Hardware IP, designed to significantly reduce memory size, DRAM bandwidth and power...
746
80.0
High Performance Scalable Sensor Hub DSP Architecture
SensPro2™ is the highly-scalable and enhanced 2nd generation high performance sensor hub DSP for multitasking sensing and AI of multiple sensors inclu...
747
80.0
LPDDR5X/5/4X combo PHY at Samsung 8LPU
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
748
80.0
LPDDR6/5X/5 combo PHY at Samsung SF4X
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
749
80.0
LPDDR6/5X/5/4X/4 Memory Controller IP
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
750
70.0
40G UCIe PHY IP on Samsung SF4X
Synopsys UCIe PHY IP enables high-bandwidth, low-power, and low-latency die-to-die connectivity in a multi-die package for hyperscale data center, AI,...