Design & Reuse
Catalog of SIP Cores
System on Chip design resources
5654 IP
1901
2.0
16-22Bit Stereo Audio CODEC with Linein/Microphone Recording, Lineout/Headphone Playback, SMIC 0.11um
The AR34S5C is a silicon-proven, low-power, ultra compact 16-22bit stereo audio CODEC IP fabricated in SMIC110nm logic process. The CODEC IP core empl...
1902
2.0
16-22Bit Stereo Audio CODEC with Microphone / Line-in Recording, Lineout / Headphone Playback, SMIC 0.13um,
The AR34S4C is a silicon-proven, low-power, ultra compact 16-22bit stereo audio CODEC IP fabricated in SMIC130nm logic process. The CODEC IP core empl...
1903
2.0
16-Bit 90dB SNR 8~48KHz stereo ADC with FM/MIC inputs, TSMC0.18um
The AR32T3D is a mass-production proven, high performance, low cost, stereo audio A/D converter designed for portable audio recording applications. Th...
1904
2.0
16-Bit 93dB Mono Sigma-Delta Audio CODEC with FM/MIC, TSMC0.18um
The AR34T3C Mono audio CODEC is a cost-down high-end solution for multi-media portable applications. It features microphone input and dual-channel hea...
1905
2.0
16-Bit >90dB SNR Stereo Audio DAC with headphone, Mono Audio ADC with microphone, Fujitsu 90nm
The AR34F5G contains a mass-production proven, low power stereo audio DAC and a mono ADC IP for portable multimedia audio applications. The IP employs...
1906
2.0
16-Bit Sigma-Delta ADC with 10 Input Channels, XFAB 0.25um
The AR32X3A specifies a silicon proven, very low power sigma-delta ADC for high-precision measurement system. The IP employs multi-bit sigma delta arc...
1907
2.0
16-Bit Sigma-Delta Stereo Audio CODEC with Microphone and Headphone, Fujitsu 65nm
The AR34F5B specifies a very low power stereo audio CODEC IP for multimedia audio system. The IP employs multibit sigma delta architecture. It include...
1908
2.0
16Bit 91dB Audio CODEC with headphone drivers and PWM Controller, SMIC0.18um
AR34S3E is a mass-production proven sigma-delta mono CODEC designed for portable device applications. It contains PWM (pulse-width-modulated) controll...
1909
2.0
16~24Bit Stereo Audio CODEC, SMIC0.18um
The AR34S1 is a 90dB multi-bit sigma-delta audio CODEC designed for low power portable applications. It requires only single 1.8V power supply to oper...
1910
2.0
Cap-less 100mA Low Noise LDO, XFAB 250nm
The LDO is capable of outputting 1.2V voltage with maximum power of 100mA and low drop out voltage of less than 200mV. The IP is fabricated in XFAB 25...
1911
2.0
Cap-less 25mA Low Noise LDO, Fujitsu 90nm
The AR25F01 is a mass-production proven cap-less LDO IP. It is capable of outputting 1.2V voltage with maximum power of 20mA and low drop out voltage ...
1912
2.0
High performance 1.8V reference current and voltage generator
The ODT-REF-16FFCT-SV1P8 is a high-performance reference current and voltage generator. The block incorporates a proprietary architecture to achieve h...
1913
2.0
Single Channel UART with Scalable Rx-FIFO
Universal asynchronous receiver and transmitter (UART) using the RS232 protocol are often used to connect peripheral devices to a central controller. ...
1914
2.0
FortifyIQ AES-SX-GCM-XTS Secure Core: High-Performance AES Encryption Core with GCM/XTS Support and Advanced SCA/FI Protection
FortifyIQ’s High-Performance AES Encryption Core is a fast, encryption-only hardware accelerator built for systems that demand secure and authenticate...
1915
2.0
FortifyIQ AES-SX-full Secure Core: High-Performance AES Encryption/Decryption Core with Advanced SCA/FI Protection
FortifyIQ’s High-Performance AES IP core delivers fast, secure AES-128/256 encryption and decryption for systems requiring high throughput and certifi...
1916
2.0
FortifyIQ AES-SX-ULP-full Secure Core: Ultra-Low-Power AES Core with Proven SCA Protection for Constrained Devices (SCA/DPA/FIA resistant)
FortifyIQ’s Ultra-Low-Power AES IP core is a compact encryption engine optimized for deeply embedded and battery-powered systems where minimizing ener...
1917
2.0
FortifyIQ AES-SX-ULP-full Secure Core: High-Performance, Ultra Low-Power AES Encryption Core with Full Mode Support and Formally Proven SCA Protection (SCA/DPA/FIA resistant)
FortifyIQ’s High-Throughput, low-power consumption AES IP core delivers AES-128/256 encryption-only with full support for ECB, CBC, CTR, GCM, and XTS ...
1918
2.0
FortifyIQ AES-SX-ULP-full Secure Core: High-Performance/Ultra Low Power AES Encryption Core with Full Mode Support and Formally Proven SCA Protection (SCA/DPA/FIA resistant)
FortifyIQ’s Ultra Low Power, High-Throughput AES IP core delivers AES-128/256 encryption-only with full support for ECB, CBC, CTR, GCM, and XTS modes,...
1919
2.0
FortifyIQ AES-SX-ULP-full Secure Core: Ultra-Low-Power AES Encryption Core with Full Mode Support and Formally Proven SCA Protection (SCA/DPA/FIA resistant)
FortifyIQ’s Low-Energy AES IP core delivers AES-128/256 encryption-only with support for all major modes, including ECB, CBC, CTR, GCM, and XTS, while...
1920
2.0
FortifyIQ Balanced AES Core with Multi-Mode Support and Advanced SCA/FI Protection
FortifyIQ’s Balanced AES IP core is a compact yet capable cryptographic accelerator designed for embedded systems with moderate performance and resour...
1921
2.0
TVM - Temperature/Voltage Monitor in 28nm CMOS
The ODT-TVM-ULP-001C-28 is an ultra-low power temperature and voltage monitor designed in a standard 28nm CMOS process. The IP operates over the entir...
1922
2.0
TVM - Temperature/Voltage Monitor in 40nm CMOS
The ODT-TVM-ULP-001C-40 is an ultra-low power temperature and voltage monitor designed in a standard 40nm CMOS process. The IP operates over the entir...
1923
1.0
1.2V Low Voltage Detector (LVD), Fujitsu 90nm
The AR22F01 is a mass-production proven low voltage detector (LVD) IP. The LVD monitors analog pad power supply levels to prevent possible damage of c...
1924
1.0
I2C Bus Interface
The serial controller interface (Single Master) core uses a two-wire bus for communicating between integrated circuits or standard peripherals like sm...
1925
1.0
I2C Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
The Digital Blocks DB-I2C-MS-AXI Controller IP Core interfaces a microprocessor via the AXI system Interconnect Fabric to an I2C Bus. The I2C is a t...
1926
1.0
14-bit, 600 MSPS Ultra Low Power ADC in 28nm CMOS
The ODT-ADP-14B600M-28 is a low power high speed pipelined ADC designed in a 28nm standard CMOS process, implemented using Omni Design's groundbreaki...
1927
1.0
Serial Controller Interface
Inicore’s iniSCI Slave is a synthesizable, flexible, and structured VHDL implementation of a Serial Controller Interface (SCI) that uses a two-wire bu...
1928
1.0
GF L013HP 130nm Clock Generator PLL - 105MHz-525MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1929
1.0
GF L013HP 130nm Clock Generator PLL - 210MHz-1050MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1930
1.0
GF L013HP 130nm Clock Generator PLL - 420MHz-2100MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1931
1.0
GF L013HP 130nm DDR DLL - 120MHz-600MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
1932
1.0
GF L013HP 130nm DDR DLL - 189MHz-945MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
1933
1.0
GF L013HP 130nm DDR DLL - 90MHz-450MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
1934
1.0
GF L013HP 130nm Deskew PLL - 105MHz-525MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1935
1.0
GF L013HP 130nm Deskew PLL - 210MHz-1050MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1936
1.0
GF L013HP 130nm Deskew PLL - 420MHz-2100MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1937
1.0
GF L013HP 130nm General Purpose PLL - 210MHz-1050MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
1938
1.0
GF L013HP 130nm Spread Spectrum PLL - 105MHz-525MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
1939
1.0
GF L013HP 130nm Spread Spectrum PLL - 210MHz-1050MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
1940
1.0
GF L013HP 130nm Spread Spectrum PLL - 420MHz-2100MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
1941
1.0
GF L013LP 130nm Clock Generator PLL - 180MHz-900MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1942
1.0
GF L013LP 130nm Clock Generator PLL - 45MHz-225MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1943
1.0
GF L013LP 130nm Clock Generator PLL - 90MHz-450MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
1944
1.0
GF L013LP 130nm DDR DLL - 39MHz-195MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
1945
1.0
GF L013LP 130nm DDR DLL - 52MHz-260MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
1946
1.0
GF L013LP 130nm DDR DLL - 82MHz-410MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
1947
1.0
GF L013LP 130nm Deskew PLL - 180MHz-900MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1948
1.0
GF L013LP 130nm Deskew PLL - 45MHz-225MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1949
1.0
GF L013LP 130nm Deskew PLL - 90MHz-450MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
1950
1.0
GF L013LP 130nm General Purpose PLL - 90MHz-450MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...