Design & Reuse
5514 IP
201
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...
202
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...
203
0.118
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process
Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...
204
0.118
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process...
205
0.118
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process
Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process...
206
0.118
DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process
DDR2 PHY Command/Address Block (for Chip Application); UMC 0.13um HS/FSG Logic Process...
207
0.118
DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process
DDR2-PHY command/address block for DRAM chip, BOAC ; UMC 90nm SP/RVT Low-K Logic Process...
208
0.118
DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process
DDR2/MDDR COMBO PHY Data block for Chip usage ; UMC 55nm SP/RVT with 2.5V device LowK Logic Process...
209
0.118
DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process
DDR2/MDDR Combo PHY for Chip load usage ; UMC 65NM SP-RVT with 2.5V device LowK Logic Process...
210
0.118
DDR34 COMBO PHY ADDR Block for Solder bump Flip chip version ;UMC 40nm LP/RVT Logic Process
DDR34 COMBO PHY ADDR Block for Solder bump Flip chip version ;UMC 40nm LP/RVT Logic Process...
211
0.118
DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process
DDRII Data Block for Chip Application; UMC 0.11um HS/AE (AL Advance Enhancement) Logic Process...
212
0.118
DDRII Data Block for Chip Application; UMC 0.13um HS/FSG Logic Process
DDRII Data Block for Chip Application; UMC 0.13um HS/FSG Logic Process...
213
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process...
214
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process...
215
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...
216
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...
217
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...
218
0.118
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application;UMC 55nm SP/RVT LowK PROCESS.
Command/Address Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application;UMC 55nm SP/RVT LowK PROCESS....
219
0.118
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process...
220
0.118
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT LowK Logic Process
Command/Address Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY supporting 2-rank application for Copper Pillar Bump Flip Chip Version; UMC 40nm LP LVT/RVT...
221
0.118
USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF
USB2.0 OTG PHY UMC 40nm LP/RVT process, for Flip chip Bump type_LF...
222
0.118
LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, for flip chip
LVDS RX IO PAD 500 Mbps, UMC 40nm LP/RVT LowK Logic Process, for flip chip...
223
0.0
UALink DL
he Chip Interfaces UA Link DL IP Core is a high-performance, silicon-agnostic and fully compliant Data Layer implementation of UALink_200 specifi cati...
224
0.0
UALink TL
The Chip Interfaces UA Link TL IP Core is a high-performance, silicon-agnostic and fully compliant Transaction Layer implementation of UALink_200 spec...
225
0.0
VeriHealth - one-stop health chip design platform
Based on VeriSilicon s own low-power IP series and advanced SoC customization technologies, VeriHealth provides a complete wearable health monitoring ...
226
0.0
JESD204E - Early adopters version
The JESD204E Controller IP from Chip Interfaces is an early adopter’s version of the upcoming revision of the JEDEC standard for Serial Interface for ...
227
0.0
BLE 5 / Sub-1GHz / 15.4/ SoC Companion Chip
A complete RF Modem companion chip for adding Bluetooth Low Energy v5.x (2.4GHz), Sub-1GHz (150-960MHz), 802.15.4(Zigbee),capability to any embedded C...
228
0.0
Ultrasound AFE Transceiver Chip for CMUT Transducers
The MVUS01 ultrasound transducer interface is the first generation of high-voltage (HV) ultrasound ASICs intended for portable medical imaging probes ...
229
0.0
Image Signal Processing (ISP) for Automotive ADAS (RPP X328)
Dream Chip’s Real-time Pixel Processor for Vision applications is a scalable and configurable High Dynamic Range (HDR) capable image signal processor ...
230
0.0
Image Signal Processing (ISP) for Automotive Vision (RPP X418)
Dream Chip’s Real-time Pixel Processor for Vision applications is a scalable and configurable High Dynamic Range (HDR) capable image signal processor ...
231
0.0
Image Signal Processing (ISP) for Industrial IoT (RPP M114)
Dream Chip’s Real-time Pixel Processor for Vision applications is a scalable and configurable Wide Dynamic Range (WDR) capable image signal processor ...
232
0.0
Image Signal Processing (ISP) for Industrial Robotics (RPP H114)
The H Series represents Dream Chip's scalable and configurable Standard Dynamic Range 12-bit ISP platform, delivering high-quality imaging with low la...
233
0.0
Image Signal Processing (ISP) for low-power Wearables / IoT (RPP H214)
The H Series represents Dream Chip's scalable and configurable Standard Dynamic Range 12-bit ISP platform, delivering high-quality imaging with low la...
234
0.0
Image Signal Processing (ISP) for Surveillance / Security (RPP W114)
The W Series represents Dream Chip's scalable and configurable Wide Dynamic Range 16-bit ISP platform, delivering high-quality imaging with low latenc...
235
0.0
XPHY Low power Chip to Chip SerDes IP, Silicon Proven in ST 28FDSOI
These IPs are targeted at applications requiring high speed, high bandwidth, low-power consumption, and low-latency interfaces....
236
0.0
TSMC CLN12FFC Chip Performance Monitor
IGACPMV08A is an on-chip performance monitor which contains a maximum of 32 customized multiple ring oscillators. This macro is one sensor unit of chi...
237
0.0
TSMC CLN5FF Chip Performance Monitor
IGACPMY01A is an on-chip performance monitor which contains a maximum of 32 customized multiple ring oscillators. This macro is one sensor unit of chi...
238
0.0
TSMC CLN7FF Chip Performance Monitor
IGACPMX01A is an on-chip performance monitor which contains a maximum of 32 customized multiple ring oscillators. This macro is one sensor unit of chi...
239
14.0
200G/400G High Speed Ethernet Controller MAC/PCS/FEC
200G/400G bandwidth solution for one Ethernet channel Cadence High Speed Ethernet Controller IP supports single channel Ethernet applications for hig...
240
14.0
400G/800G High Speed Ethernet Controller MAC/PCS/FEC
800G/400G bandwidth solution for one Ethernet channel Cadence High Speed Ethernet Controller IP supports single channel Ethernet applications for hig...
241
14.0
400G/800G High Speed Ethernet Controller PCS/FEC
Up to 800G bandwidth solution for one Ethernet channel Cadence High Speed Ethernet Controller IP supports single channel Ethernet applications for hi...
242
14.0
10G to 100G High Speed Ethernet Controller MAC/PCS/FEC
Up to 100G bandwidth solution for one Ethernet channel Cadence High Speed Ethernet Controller IP supports single channel Ethernet applications for hi...
243
14.0
10G to 400G High Speed Channelized Ethernet Controller MAC/PCS/FEC
400G aggregate bandwidth channelized solution for up to eight Ethernet channels Cadence High Speed Ethernet Controller IP supports multi-channel Ethe...
244
14.0
10G to 400G High Speed Ethernet Controller MAC/PCS/FEC
Up to 400G bandwidth solution for one Ethernet channel Cadence High Speed Ethernet Controller IP supports single channel Ethernet applications for hi...
245
14.0
40G Ultralink D2D PHY for GF12LP+
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
246
14.0
40G Ultralink D2D PHY for GF12LP+
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
247
14.0
40G Ultralink D2D PHY for Samsung 7LPP
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
248
14.0
40G Ultralink D2D PHY for Samsung 7LPP
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
249
14.0
10G/2.5G/1G Multi-Speed Ethernet Controller IP for Automotive Applications
Configurable MAC solutions for speeds from 10Gbps to 10Mbps The Cadence 10G/2.5G/1G Multi-Speed Ethernet Controller IP for Automotive Applications is...
250
14.0
10G/2.5G/1G Multi-Speed Ethernet Controller IP for Automotive Applications
Configurable MAC solutions for speeds from 10Gbps to 10Mbps The Cadence 10G/2.5G/1G Multi-Speed Ethernet Controller IP for Automotive Applications is...