Design & Reuse
4951 IP
2001
1.0
GF L90G 90nm DDR DLL - 93MHz-465MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2002
1.0
GF L90G 90nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2003
1.0
GF L90G 90nm Deskew PLL - 240MHz-1200MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2004
1.0
GF L90G 90nm Deskew PLL - 60MHz-300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2005
1.0
GF L90G 90nm General Purpose PLL - 120MHz-600MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
2006
1.0
GF L90G 90nm Spread Spectrum PLL - 120MHz-600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2007
1.0
GF L90G 90nm Spread Spectrum PLL - 240MHz-1200MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2008
1.0
GF L90G 90nm Spread Spectrum PLL - 60MHz-300MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2009
1.0
GF L90GOD 90nm Clock Generator PLL - 180MHz-900MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2010
1.0
GF L90GOD 90nm Clock Generator PLL - 360MHz-1800MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2011
1.0
GF L90GOD 90nm Clock Generator PLL - 90MHz-450MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2012
1.0
GF L90GOD 90nm DDR DLL - 129MHz-645MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2013
1.0
GF L90GOD 90nm DDR DLL - 172MHz-860MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2014
1.0
GF L90GOD 90nm DDR DLL - 272MHz-1360MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2015
1.0
GF L90GOD 90nm Deskew PLL - 180MHz-900MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2016
1.0
GF L90GOD 90nm Deskew PLL - 360MHz-1800MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2017
1.0
GF L90GOD 90nm Deskew PLL - 90MHz-450MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2018
1.0
GF L90GOD 90nm General Purpose PLL - 180MHz-900MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
2019
1.0
GF L90GOD 90nm Spread Spectrum PLL - 180MHz-900MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2020
1.0
GF L90GOD 90nm Spread Spectrum PLL - 360MHz-1800MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2021
1.0
GF L90GOD 90nm Spread Spectrum PLL - 90MHz-450MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2022
1.0
GF L90LP 90nm Clock Generator PLL - 150MHz-750MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2023
1.0
GF L90LP 90nm Clock Generator PLL - 300MHz-1500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2024
1.0
GF L90LP 90nm Clock Generator PLL - 75MHz-375MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2025
1.0
GF L90LP 90nm DDR DLL - 124MHz-620MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2026
1.0
GF L90LP 90nm DDR DLL - 196MHz-980MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2027
1.0
GF L90LP 90nm DDR DLL - 93MHz-465MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2028
1.0
GF L90LP 90nm Deskew PLL - 150MHz-750MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2029
1.0
GF L90LP 90nm Deskew PLL - 300MHz-1500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2030
1.0
GF L90LP 90nm Deskew PLL - 75MHz-375MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2031
1.0
GF L90LP 90nm General Purpose PLL - 150MHz-750MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
2032
1.0
GF L90LP 90nm Spread Spectrum PLL - 150MHz-750MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2033
1.0
GF L90LP 90nm Spread Spectrum PLL - 300MHz-1500MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2034
1.0
GF L90LP 90nm Spread Spectrum PLL - 75MHz-375MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2035
1.0
RF SP3T Switch used in TDD (Time Division Duplexing) mode for switching between TX and RX path with low loss, broadband and high isolation
RFSW02C RF SP3T Switch is used in TDD (Time Division Duplexing) mode for switching between TX and RX path with low loss, broadband and high isolation....
2036
1.0
RF SPDT Switch from 10-30 GHz used in TDD (Time Division Duplexing) mode for switching between TX and RX path with low loss, broadband and high isolation
RFSW01C RF SPDT Switch is used in TDD (Time Division Duplexing) mode for switching between TX and RX path with low loss, broadband and high isolation....
2037
1.0
RF SPDT Switch from 2-44 GHz used in TDD (Time Division Duplexing) mode for switching between TX and RX path with low loss, broadband and high isolation
RFSW03C RF SPDT Switch is used in TDD (Time Division Duplexing) mode for switching between TX and RX path with low loss, broadband and high isolation....
2038
1.0
RF SPDT Switch from 20-40 GHz used in TDD (Time Division Duplexing) mode for switching between TX and RX path with low loss, broadband and high isolation
RFSW05C RF SPDT Switch is used in TDD (Time Division Duplexing) mode for switching between TX and RX path with low loss, broadband and high isolation....
2039
1.0
RF SPDT Switch from 20-40 GHz used in TDD (Time Division Duplexing) mode for switching between TX and RX path with low loss, broadband and high isolation
RFSW04C RF SPDT Switch is used in TDD (Time Division Duplexing) mode for switching between TX and RX path with low loss, broadband and high isolation....
2040
1.0
2GHz-6GHz High Efficiency Broadband Low Noise Amplifier
The RS03 is 2 to 6 GHz; high efficiency Broadband Single Stage Low noise amplifier, designed on 0.35-ìm SiGe BiCMOS technology. The device is designed...
2041
1.0
2GHz-6GHz Low noise amplifier
...
2042
1.0
2GHz-6GHz Voltage Controlled Oscillator
RJVC02 is 2.0 - 6.0 GHz, voltage controlled oscillator. It can operate at 1.8 V supply and consumes only 1.0 mA current. The tuning bandwidth of the o...
2043
1.0
SiGe BiCMOS WCDMA Power Amplifier
The RJP01 is 1.920 to 1.980 GHz high efficiency WCDMA Power Amplifier. The Amplifier is designed using 0.18 um SiGe BiCMOS technology. Power amplifier...
2044
1.0
SiGe BiCMOS WLAN Power Amplifier
The RJP05 is 2.4 GHz to 2.5 GHz; high efficiency Power stage for WLAN Power Amplifier. The Amplifier is designed using 0.18um SiGe BiCMOS process for ...
2045
1.0
High-Performance, Configurable, 8-bit Microcontroller Core
This 8051 IP core implements a range of fast, 8-bit, 8051-compatible microcontrollers that execute the MCS®51 instruction set. The R8051XC2 IP core r...
2046
1.0
Single stage low noise amplifier from 2-6 GHz with flat gain, low Noise Figure, high isolation, stability.
RFLN04C is a single stage low noise amplifier with flat gain, low Noise Figure, high isolation, stability. The LNA is designed to operate from 2-6 GHz...
2047
1.0
BitBLT Graphics Hardware Accelerator (AHB Bus)
The Digital Blocks DB9100AHB BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to ...
2048
1.0
BitBLT Graphics Hardware Accelerator (AXI Bus)
The Digital Blocks DB9100AXI3 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to...
2049
1.0
Ultra-Small 8051-Compatible Microcontroller
The T8051XC3 core implements one of the smallest-available 8-bit MCS®51-compatible microcontrollers. The core integrates an 8051 CPU with a serial com...
2050
1.0
UMC L130HS 130nm Clock Generator PLL - 160MHz-800MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...