Arasan Chip Systems Inc. IP Cores

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2201

1.0

UMC L80G 80nm Clock Generator PLL - 120MHz-600MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2202

1.0

UMC L80G 80nm Clock Generator PLL - 240MHz-1200MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2203

1.0

UMC L80G 80nm Clock Generator PLL - 480MHz-2400MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2204

1.0

UMC L80G 80nm DDR DLL - 129MHz-645MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2205

1.0

UMC L80G 80nm DDR DLL - 172MHz-860MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2206

1.0

UMC L80G 80nm Deskew PLL - 120MHz-600MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2207

1.0

UMC L80G 80nm Deskew PLL - 240MHz-1200MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2208

1.0

UMC L80G 80nm Deskew PLL - 480MHz-2400MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2209

1.0

UMC L80G 80nm Spread Spectrum PLL - 120MHz-600MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2210

1.0

UMC L80G 80nm Spread Spectrum PLL - 240MHz-1200MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2211

1.0

UMC L80G 80nm Spread Spectrum PLL - 480MHz-2400MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2212

1.0

UMC L80GOD 80nm Clock Generator PLL - 150MHz-750MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2213

1.0

UMC L80GOD 80nm Clock Generator PLL - 300MHz-1500MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2214

1.0

UMC L80GOD 80nm Clock Generator PLL - 600MHz-3000MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2215

1.0

UMC L80GOD 80nm DDR DLL - 150MHz-750MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2216

1.0

UMC L80GOD 80nm DDR DLL - 200MHz-1000MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2217

1.0

UMC L80GOD 80nm Deskew PLL - 150MHz-750MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2218

1.0

UMC L80GOD 80nm Deskew PLL - 300MHz-1500MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2219

1.0

UMC L80GOD 80nm Deskew PLL - 600MHz-3000MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2220

1.0

UMC L80GOD 80nm Spread Spectrum PLL - 150MHz-750MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2221

1.0

UMC L80GOD 80nm Spread Spectrum PLL - 300MHz-1500MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2222

1.0

UMC L80GOD 80nm Spread Spectrum PLL - 600MHz-3000MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2223

1.0

UMC L90G 90nm Clock Generator PLL - 180MHz-900MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2224

1.0

UMC L90G 90nm Clock Generator PLL - 360MHz-1800MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2225

1.0

UMC L90G 90nm Clock Generator PLL - 90MHz-450MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2226

1.0

UMC L90G 90nm DDR DLL - 108MHz-540MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2227

1.0

UMC L90G 90nm DDR DLL - 144MHz-720MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2228

1.0

UMC L90G 90nm Deskew PLL - 180MHz-900MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2229

1.0

UMC L90G 90nm Deskew PLL - 360MHz-1800MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2230

1.0

UMC L90G 90nm Deskew PLL - 90MHz-450MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2231

1.0

UMC L90G 90nm Spread Spectrum PLL - 180MHz-900MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2232

1.0

UMC L90G 90nm Spread Spectrum PLL - 360MHz-1800MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2233

1.0

UMC L90G 90nm Spread Spectrum PLL - 90MHz-450MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2234

1.0

UMC L90GOD 90nm Clock Generator PLL - 125MHz-625MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2235

1.0

UMC L90GOD 90nm Clock Generator PLL - 250MHz-1250MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2236

1.0

UMC L90GOD 90nm Clock Generator PLL - 500MHz-2500MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2237

1.0

UMC L90GOD 90nm DDR DLL - 144MHz-720MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2238

1.0

UMC L90GOD 90nm DDR DLL - 192MHz-960MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2239

1.0

UMC L90GOD 90nm Deskew PLL - 125MHz-625MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2240

1.0

UMC L90GOD 90nm Deskew PLL - 250MHz-1250MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2241

1.0

UMC L90GOD 90nm Deskew PLL - 500MHz-2500MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2242

1.0

UMC L90GOD 90nm Spread Spectrum PLL - 125MHz-625MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2243

1.0

UMC L90GOD 90nm Spread Spectrum PLL - 250MHz-1250MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2244

1.0

UMC L90GOD 90nm Spread Spectrum PLL - 500MHz-2500MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2245

1.0

UMC L90SP 90nm Clock Generator PLL - 120MHz-600MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2246

1.0

UMC L90SP 90nm Clock Generator PLL - 240MHz-1200MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2247

1.0

UMC L90SP 90nm Clock Generator PLL - 60MHz-300MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2248

1.0

UMC L90SP 90nm DDR DLL - 60MHz-300MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2249

1.0

UMC L90SP 90nm DDR DLL - 80MHz-400MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2250

1.0

UMC L90SP 90nm Deskew PLL - 120MHz-600MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

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