Design & Reuse
Catalog of SIP Cores
System on Chip design resources
5620 IP
251
0.0
Ethernet MAC 100G/200G/400G/800G/1.6T
The Chip Interfaces 100G/200G/400G/800/1.6T Ethernet Media Access Control (MAC) IP core provides a comprehensive and flexible solution for implementin...
252
0.0
Ethernet PCS 100G/200G/400G/800G/1.6T
Chip Interfaces 100G-1.6T Ethernet PCS IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) described in the Ethernet st...
253
200.0
224G-LR SerDes PHY for UALink for TSMC
224G-LR SerDes PHY enables 1.6T and 800G networks for UALink UALink, the standard for AI accelerator interconnects, facilitates this scalability by...
254
150.0
DDR5 MRDIMM for TSMC
Lowest latency and highest data rates for data-intensive applications Cadence Design IP solutions offer world-class DDR PHY and controller memory I...
255
150.0
PHY for PCIe 7.0 for TSMC
The Cadence PHY IP for PCI Express (PCIe) 7.0 delivers a data rate of up to 128Gbps in PAM4 mode. Designed specifically for Infrastructure and data ce...
256
150.0
High Bandwidth Memory (HBM4E) PHY for TSMC
Designed for performance and low latency in AI/ML, HPC, data center and graphics applications The High-Bandwidth Memory generation (HBM4/4E) PHY is...
257
150.0
UltraLink Controller
Ultralink controller for high performance die-to-die interconnect on streaming, CXS, and AXI protocols The Cadence Ultralink Controller enables a p...
258
150.0
LPDDR6/5X Memory PHY for TSMC
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
259
150.0
eUSB2V2 PHY for TSMC
Low voltage USB 2.0 supporting 4.8Gbps eUSB2V2 is primarily a performance enhancement to eUSB2 native mode to provide more bandwidth for peripheral...
260
100.0
224G-LR SerDes PHY for TSMC
224G-LR SerDes PHY enables 1.6T and 800G networks The ever-increasing bandwidth in high-performance computing (HPC) applications is driving the rap...
261
75.0
64G UCIe Standard PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
262
75.0
PCI Express (PCIe) 7.0 Controller
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 7.0 provides the logic required to integrate a r...
263
75.0
PHY for PCIe 6.0 and CXL for TSMC
Most advanced PHY and Controller for HPC, AI, ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®)...
264
75.0
LPDDR6/5X Memory PHY for Samsung
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
265
50.0
112G-VSR for TSMC
112G-VSR Serdes PAM4 PHY Enables reliable high-speed data transfer over backplane, DAC, chip-to-chip, and chip-to-module channel The Cadence 112Gbp...
266
50.0
PHY for PCIe 5.0 and CXL for Samsung
Cadence 32G NRZ multi-;protocol PHY The Cadence 32G Multi-Protocol PHY IP for Samsung is a high--performance SerDes operating from 1.25Gbps to 32Gb...
267
50.0
PHY for PCIe 5.0 and CXL for TSMC
Cadence 32G NRZ multi-;protocol PHY The Cadence 32G Multi-Protocol PHY IP for TSMC is a high--performance SerDes operating from 1.25Gbps to 32Gbps ...
268
25.0
32G UCIe Advanced PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
269
25.0
PCI Express (PCIe) 6.0 Controller
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 6.0 provides the logic required to integrate a r...
270
25.0
PHY for PCIe 6.0 and CXL for Intel 18A
Most advanced PHY and Controller for HPC, AI, ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®)...
271
25.0
PHY for PCIe 6.0 and CXL for Samsung
Most advanced PHY and Controller for HPC, AI, ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®)...
272
25.0
High Bandwidth Memory (HBM3E) PHY for TSMC
Designed for performance and low latency in AI/ML, HPC, data center and graphics applications The High-Bandwidth Memory generation 3 (HBM3E) PHY is...
273
15.0
32G UCIe Standard PHY for Samsung
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
274
15.0
32G UCIe Standard PHY for TSMC
UCIe enables chiplet industry standard interoperability combined with ultra-low latency, extreme power efficiency, and high performance. The Cadenc...
275
15.0
PCI Express (PCIe) 5.0 Controller
Application-optimized, high-performance controller IP for PCIe The Cadence® Controller IP for PCIe 5.0 provides the logic required to integrate a r...
276
15.0
PCIe 3.1 for TSMC
Optimized for power and area, our line-up of SerDes PHYs, deliver maximum performance and flexibility for today's most challenging designs. The 8Gb...
277
15.0
PHY for PCIe 6.0 and CXL for Samsung Automotive
Most advanced PHY and Controller for HPC, AI, ML, Data communications, networking, and storage systems The Cadence® PHY IP for PCI Express® (PCIe®)...
278
15.0
LPDDR5/5X Memory PHY for Samsung
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
279
14.0
40G Ultralink D2D PHY for GF12LP+
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
280
14.0
40G Ultralink D2D PHY for GF12LP+
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
281
14.0
40G Ultralink D2D PHY for Samsung 7LPP
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
282
14.0
40G Ultralink D2D PHY for Samsung 7LPP
Proprietary chiplet interconnect solution with high-performance, high-bandwidth, and long reach die-to-die link connectivity The Cadence® UltraLink™ ...
283
14.0
10G/2.5G/1G Multi-Speed Ethernet Controller IP for Automotive Applications
Configurable MAC solutions for speeds from 10Gbps to 10Mbps The Cadence 10G/2.5G/1G Multi-Speed Ethernet Controller IP for Automotive Applications is...
284
14.0
10G/2.5G/1G Multi-Speed Ethernet Controller IP for Automotive Applications
Configurable MAC solutions for speeds from 10Gbps to 10Mbps The Cadence 10G/2.5G/1G Multi-Speed Ethernet Controller IP for Automotive Applications is...
285
14.0
10Gbps Multi-Protocol PHY IP
Silicon-proven PHY for PCIe, USB, Ethernet, DisplayPort, and other protocols The PHY IP is designed to deliver high eye-margin at low power for backp...
286
14.0
Denali Controller for DDR
LPDDR5/4X/4/3 and DDR5/4/3L/3, to 6400Mbps and beyond The Cadence Denali Controller IP for LPDDR5/4X/4/3 and DDR5/4/3L/3 provides low latency and u...
287
14.0
Denali Controller for GDDR6
GDDR6 devices to 16Gbps, 18Gbps, 20Gbps, and beyond The latest, the Cadence Denali Controller IP for GDDR6, provides low latency and very high bandwi...
288
14.0
Denali DDR PHY for TSMC
LPDDR4/3, DDR4/3/3L, up to 4266Mbps The latest Denali high-speed DDR PHY IP is comprised of architectural improvements to its highly successful pre...
289
14.0
Denali High-Speed DDR PHY for UMC
Provides the industry's highest data rates with low-latency througput while balancing power consumption and minimizing area Developed by experience...
290
14.0
Tensilica ConnX 110/120
Compact and low energy consumption to provide the performance you need in radar, lidar, and communications processing at ultra-l Cadence Tensilica Co...
291
14.0
Universal Chiplet Interconnect Express (UCIe 1.0) Controller
Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller i...
292
14.0
Universal Chiplet Interconnect Express (UCIe 1.0) Controller
Ultra-low latency UCIe controller for standard industry chiplet interoperability on streaming, PCIe, and CXL protocols The Cadence UCIe™ Controller i...
293
10.0
LPDDR5/4X PHY IP for TSMC
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
294
8.0
FortifyIQ's Secure Hybrid Crypto Box IP Core with Classical and Post-Quantum Cryptography for Embedded Systems (AES, HMAC-SHA2, ECC/RSA etc., PQC) (SCA,DPA,FIA secure)
FortifyIQ’s Hybrid Crypto Box IP core is a comprehensive, high-efficiency cryptographic solution that combines RSA, ECC, AES, and SHA-2/HMAC with a bu...
295
6.0
I2C Master/Slave Controller Core IP
I2C Master/Slave Controller core implements a bidirectional serial interface compatible with the NXP’s I2C bus specification and supports all transfer...
296
6.0
UART : Universal Asynchronous Receiver Transmitter Core
Universal Asynchronous Receiver Transmitter Core performs serial-to-parallel conversion on data characters received from a peripheral device or a MODE...
297
6.0
SD Memory Card Host Controller
VinSDHC3_0 SD Host Controller Core controls data transfers between the SD Host System and the SD Memory Card sockets. It is compliant with the standar...
298
6.0
AHB To PCI Wrapper
VinChip’s AHB to PCI wrapper can be used to verify AHB (AMBA) based systems on a PCI environment for ease of debugging the target hardware and it can ...
299
6.0
Embedded Host Controller 1. 1
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300
6.0
Embedded Host Controller 2.0
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