Design & Reuse
4953 IP
3401
0.0
RISC-V processor with vector extension certified for ISO 26262 ASIL D ready
Off-loading heavy calculations from microcontrollers The DR1000C is a parallel processor IP that is ideal for offloading high-load arithmetic process...
3402
0.0
Display Stream Compression (DSC 1.2) Decoder
The Trilinear Technologies Display Stream Compression (DSC) Decoder core offers realtime decompression of high-definition streams with resolutions fro...
3403
0.0
Display Stream Compression (DSC 1.2) Encoder
The Trilinear Technologies Display Stream Compression (DSC) Encoder offers real-time compression of high-definition streams with resolutions up to 8K....
3404
0.0
DisplayPort 1.4 Transmitter Link Controller
Continuing the highly successful line of DisplayPort link controller cores, the Trilinear VF-111T DisplayPort Transmitter core has been updated to inc...
3405
0.0
DisplayPort Receiver Link Controller
Our 5th generation DisplayPort Receiver Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link rate...
3406
0.0
DisplayPort Transmitter Link Controller
Our 5th generation DisplayPort Transmitter Link Controller core supports DisplayPort 1.4, 2.0 and embedded DisplayPort 1.4b features, including link r...
3407
0.0
VisualSim AI Evaluator
VisualSim AI Evaluator is an AI evaluator that combines analog, digital, power and network modeling to select the right architecture for the accelerat...
3408
0.0
VisualSim Artificial Intelligence (AI)-driven Processor Generator
VisualSim Processor Generator is a revolutionary and extremely intelligent library. The library contains the generators and a large set of pre-define...
3409
0.0
VisualSim Explorer
VisualSim Explorer is a Web Server that enables models to be embedded in documents for viewing, simulation and analysis from within a Web Browser with...
3410
0.0
BitBLT Graphics Hardware Accelerator (AXI4 Bus)
The Digital Blocks DB9100AXI4 BitBLT Graphics Hardware Accelerator Verilog IP Core renders a graphics frame by generating new bitmaps from commands to...
3411
0.0
BitBLT Graphics Hardware Accelerator Engine
The DB9100 BitBLT 2D Graphics Engine IP Core (Verilog Cores DB9100AXI4, DB9100AXI, DB9100AHB, DB9100AVLN) reads graphics command sets originated by th...
3412
0.0
Mixel, Inc.- Mixed-signal IP
Mixel is focused on providing intellectual property cores and design services in the mixed-signal IC area. Mission Statement Provide our custom...
3413
0.0
All Digital Phase Locked Loop
The iniADPLL is an all digital implementation of a phase locked loop. Plls are widely used in telecom applications for clock recovery, clock generatio...
3414
0.0
Clock Delay Monitor IP
Synopsys’ Clock and Delay Monitor (CDM) is a small IP capable of performing on-chip measurements, monitoring, and safety operations. It can be embedde...
3415
0.0
Clock/Data Recovery PLL
The MXL-PLL-CDR is a clock/data recovery PLL implemented using a digital CMOS process. It is highly integrated and require no external components. Dif...
3416
0.0
Alphacore ASIC Design Services
The Alphacore ASIC design team has extensive experience in delivering complete low power, high speed analog mixed signal, imaging, power management, a...
3417
0.0
Ultra Accelerator Link（UALink) Controller
Full-stack, scalable, configurable UALink Transaction Layer (TL), Data Link Layer (DL), and Physical Layer (PL), interconnect IP for next-generation A...
3418
0.0
Ultra Low Power Edge AI Processor
DMP AI processor IP, ZIA™ DV740, is the ultra low power consumption processor IP for Deep Learning on edge side specialized on inference processing. Z...
3419
0.0
Bluetooth 5.2 / 5.1 / 5.0 / 4.2 LE Controller with Link Layer and optional 802.15.4 MAC
Packetcraft's Bluetooth 5.2 / 5.1 / 5.0 / 4.2 Low Energy Controller IP, (PC-BLE-C5.2), is a highly optimized, comprehensive and flexible solution for ...
3420
0.0
SM3 Crypto Accelerator
The EIP-52 SM3 Engine implements the SM3 hash algorithm. The accelerators include I/O registers, hash calculation cores, message padding logic, and da...
3421
0.0
SM4 Crypto Accelerator
The EIP-12 SM4 Engine implements the SM4 cipher block algorithm. The accelerator includes I/O registers, encryption and decryption cores. Designed for...
3422
0.0
SM4-XTS Crypto Accelerator
The EIP-312 – SM4-XTS Accelerator is specifically suited for next generation processors deployed in networking and storage appliances and SSD controll...
3423
0.0
DMA AXI4-Stream Interface to AXI Memory Map Address Space
Digital Blocks DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE Verilog RTL IP Core accepts AXI4-Stream data and control input, converts the control TID to a AXI4 Mem...
3424
0.0
HMAC Accelerator with SHA-3, SHA-2, SHA-1
The EIP-59 is the IP for accelerating the various single pass HMAC (FIPS-198-1) algorithms using secure hash integrity algorithms like MD5 (RFC1231),...
3425
0.0
CMAC and XCBC AES Core
The CMAC1 core provides implementation of cryptographic hashes AES-CMAC per NIST SP 800-38B and AES-XCBC. The cores utilize “flow-through” design that...
3426
0.0
HMAC-SHA-2 (224/256/384/512) 100 Million Trace DPA Resistant Crypto Accelerato
Rambus DPA Resistant HMAC-SHA-2 Cryptographic Accelerator Cores prevent against the leakage of secret cryptographic key material through attacks when ...
3427
0.0
Small and Fast Security Solutions for Critical Automotive Applications
Today's vehicles are equipped with multiple microcontrollers that control critical safety and performance functions in a vehicle. When considering...
3428
0.0
AMBA AHB Device/Host Bridge
This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices. The bridge supports Hos...
3429
0.0
AMBA AHB to APB Bus Bridge Core
The AHB2APB implements an AHB to APB bus bridge, allowing the connection of peripherals with an APB interface to an AHB bus. The highly-configurable...
3430
0.0
AMBA AHB Verification IP
AMBA AHB VIP can be configured as Master, Slave and AHB bus and allows Module & System level verification. AMBA AHB VIP is a readymade highly configur...
3431
0.0
AMBA AXI 4.0 Verification IP
eInfochips’ AXI 4.0 Verification IP Product is the Industry’s most comprehensive protocol validation solution for predictable verification of AMBA AXI...
3432
0.0
Embedded Memories for GF (55nm, 40nm, 22nm)
Synopsys provides the industry's broadest portfolio of silicon-proven foundation IP, including Memory Compilers, Logic Libraries and General Purpose I...
3433
0.0
Embedded Memories for Intel (16nm, 18A)
Synopsys provides the industry's broadest portfolio of silicon-proven foundation IP, including Memory Compilers, Logic Libraries and General Purpose I...
3434
0.0
Embedded Memories for SMIC (65nm, 40nm)
Synopsys provides the industry's broadest portfolio of silicon-proven foundation IP, including Memory Compilers, Logic Libraries and General Purpose I...
3435
0.0
Embedded Memories for TSMC (65nm, 40nm, 28nm, 22nm, 16nm, N7, N4, N3)
Synopsys provides the industry's broadest portfolio of silicon-proven foundation IP, including Memory Compilers, Logic Libraries and General Purpose I...
3436
0.0
Embedded Memories for UMC (40nm, 28nm)
Synopsys provides the industry's broadest portfolio of silicon-proven foundation IP, including Memory Compilers, Logic Libraries and General Purpose I...
3437
0.0
UMC L110AELL 110nm Clock Generator PLL - 120MHz-600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
3438
0.0
UMC L110AELL 110nm Clock Generator PLL - 30MHz-150MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
3439
0.0
UMC L110AELL 110nm Clock Generator PLL - 60MHz-300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
3440
0.0
UMC L110AELL 110nm DDR DLL - 24MHz-120MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
3441
0.0
UMC L110AELL 110nm DDR DLL - 32MHz-160MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
3442
0.0
UMC L110AELL 110nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3443
0.0
UMC L110AELL 110nm Deskew PLL - 30MHz-150MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3444
0.0
UMC L110AELL 110nm Deskew PLL - 60MHz-300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3445
0.0
UMC L110AELL 110nm Spread Spectrum PLL - 120MHz-600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
3446
0.0
UMC L110AELL 110nm Spread Spectrum PLL - 30MHz-150MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
3447
0.0
UMC L110AELL 110nm Spread Spectrum PLL - 60MHz-300MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
3448
0.0
UMC L110HS 110nm Clock Generator PLL - 160MHz-800MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
3449
0.0
UMC L110HS 110nm Clock Generator PLL - 320MHz-1600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
3450
0.0
UMC L110HS 110nm Clock Generator PLL - 80MHz-400MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...