Design & Reuse
Catalog of SIP Cores
System on Chip design resources
5494 IP
4301
0.0
LPDDR Controller ASIL B Compliant for LPDDR5/4/4X for Automotive Applications
Synopsys LPDDR5/4/4X Controller is a next-generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5, L...
4302
0.0
LPDDR Controller ASIL B Compliant for LPDDR5X/5/4X for automotive
Synopsys LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5X,...
4303
0.0
LPDDR Controller for LPDDR5X, LPDDR5 and LPDDR4X
Synopsys LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5X,...
4304
0.0
LPDDR4 multiPHY V2 in UMC (28nm)
The Synopsys LPDDR4 multiPHY is Synopsys’ second generation physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and sy...
4305
0.0
LPDDR4X / LPDDR4 Controller
The Rambus LPDDR4X/4 controller core is designed for use in applications requiring high memory throughput at low power including mobile, Internet of ...
4306
0.0
LPDDR4X/4/3/DDR4 PHY for TSMC
Lowest latency and highest data rates for data-intensive applications Developed by experienced teams with industry-leading domain expertise and ext...
4307
0.0
LPDDR4X/4/3/DDR4 PHY for TSMC 12nm and 16nm
Lowest latency and highest data rates for data-intensive applications Developed by experienced teams with industry-leading domain expertise and ext...
4308
0.0
LPDDR4X/4/3/DDR4 PHY for UMC
Lowest latency and highest data rates for data-intensive applications Developed by experienced teams with industry-leading domain expertise and ext...
4309
0.0
LPDDR5/4/4X Controller with Inline Memory Encryption (IME) Security Module
SynopsysLPDDR5/4/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5, LP...
4310
0.0
LPDDR5/4X COMBO PHY 7nm/6nm
The LPDDR5 and LPDDR4x Combo PHY is designed for easy integration into any System-On-Chip (SOC) and can be seamlessly connected with a third-party DFI...
4311
0.0
LPDDR5/4X PHY IP for TSMC
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
4312
0.0
LPDDR5/4X PHY IP for TSMC N7
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
4313
0.0
LPDDR5/5X Memory PHY for Intel
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
4314
0.0
LPDDR5/5X Memory PHY for Samsung
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
4315
0.0
LPDDR5/5X Memory PHY for TSMC
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
4316
0.0
LPDDR5/5X Memory PHY for TSMC N3P
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
4317
0.0
LPDDR5/5X Memory PHY for TSMC N4P
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
4318
0.0
LPDDR5/5X Memory PHY for TSMC N5P
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
4319
0.0
LPDDR5X 7nm/6nm PHY
The InPsytech LPDDR5x PHY is a high-performance, low-power physical interface IP designed for seamless integration into any System-on-Chip (SoC). It c...
4320
0.0
LPDDR5X PHY 3nm
The InPsytech LPDDR5x PHY is a high-performance, low-power physical interface IP designed for seamless integration into any System-on-Chip (SoC). It c...
4321
0.0
LPDDR5X PHY 5nm/4nm
The InPsytech LPDDR5x PHY is a high-performance, low-power physical interface IP designed for seamless integration into any System-on-Chip (SoC). It c...
4322
0.0
LPDDR5X/5/4X COMBO PHY
The LPDDR5x, LPDDR5, and LPDDR4x Combo PHY is designed for seamless integration into any System-on-Chip (SoC) and can easily connect to a third-party ...
4323
0.0
LPDDR5X/5/4X Controller with Inline Memory Encryption (IME) Security Module
Synopsys LPDDR5X/5/4X Controller is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR5X,...
4324
0.0
LPDDR5X/5/4X PHY in Samsung (SF4A, SF2A) For Automotive
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...
4325
0.0
LPDDR5X/5/4X PHY IP in Samsung (SF5A) for Automotive
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-inpackage ap...
4326
0.0
LPDDR5X/5/4X PHY IP on TSMC N3P
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...
4327
0.0
LPDDR5X/5/4X PHY on TSMC N5A for Automotive
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system-inpackage ap...
4328
0.0
LPDDR6/5X Memory PHY for Rapidus
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
4329
0.0
LPDDR6/5X Memory PHY for Samsung
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
4330
0.0
LPDDR6/5X Memory PHY for TSMC
Lowest latency and highest data rates for data-intensive applications The LPDDR PHY IP is comprised of architectural improvements to its highly suc...
4331
0.0
LPDDR6/5X/5 Controller IP
Synopsys LPDDR6/5X/5 Controller IP is a next generation controller optimized for power, latency, bandwidth, and area, supporting JEDEC standard LPDDR6...
4332
0.0
LPDDR6/5X/5 PHY in TSMC (N3P, N2P)
The Synopsys LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LP...
4333
0.0
LPDDR6/5X/5 PHY V2 in Samsung (SF2A, SF4A) for Automotive
The Synopsys LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LP...
4334
0.0
LPDDR6/5X/5 PHY V2 in Samsung (SF2P, SF4X)
The Synopsys LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LP...
4335
0.0
LPDDR6/5X/5 PHY V2 in TSMC (N5A, N3A) for Automotive
The Synopsys LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LP...
4336
0.0
LPDDR6/5X/5 PHY V2 in TSMC (N6, N6C, N5, N4P, N4C, N3P, N2P)
The Synopsys LPDDR6/5X/5 PHY IP enables ASICs, ASSPs, system-on-chips (SoCs), and system-in-package applications requiring high-performance LPDDR6, LP...
4337
0.0
MPEG Transport Stream Multiplexing & Encapsulation Engine
The MTS-E core multiplexes and encapsulates audio, video and metadata streams in a single MPEG Transport Stream (TS), and optionally encapsulates the ...
4338
0.0
SPI Master / Slave Controller w/FIFO (AHB & AHB-Lite Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
4339
0.0
SPI Master / Slave Controller w/FIFO (AXI & AXI-Lite Bus)
The Digital Blocks DB-SPI-MS is a Serial Port Interface (SPI) Controller Verilog IP Core supporting both Master/Slave SPI Bus transfers. The DB-SPI-MS...
4340
0.0
SPI Master Controller w/FIFO (AHB & AHB-Lite Bus)
The Digital Blocks DB-SPI-M is a Serial Port Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and...
4341
0.0
SPI Master Controller w/FIFO (APB Bus)
The Digital Blocks DB-SPI-M is a Serial Port Interface (SPI) Controller Verilog IP Core supporting only Master SPI Bus transfers (both Full Duplex and...
4342
0.0
SPI to AHB Lite Bridge
The ISPI Slave to AHB Lite Master is commonly used as a monitor interface to allow external devices to access the internal AHB bus. A SPI Slave to ...
4343
0.0
SPI to AXI Bridge
The AHB Lite to AXI Bridge translates an AHB Lite bus transaction (read or write) to an AXI bus transaction. It is expected that the AXI clock and th...
4344
0.0
SPI-3 Link Layer eVerification Component
...
4345
0.0
SPI-3 PHY Layer eVerification Component
...
4346
0.0
Spread Spectrum PLL
The MXL-PLL-SS-R is a high performance PLL based Spread Spectrum Clock Generator implemented using a digital CMOS technology. It is highly integrated...
4347
0.0
IPsec Security Processor
Core implements the IPsec and SSL/TLS security standard at high data rates that require the cryptographic processing acceleration. The ISP1-128 core i...
4348
0.0
IPsec Security Processor
Core implements the IPsec and SSL/TLS security standard at high data rates that require the cryptographic processing acceleration. The ISP1-128 core i...
4349
0.0
IPsec software toolkit
The Rambus IPsec Toolkit (previously QuickSec from Inside Secure) is client/server software for cloud and embedded security. It provides a complete so...
4350
0.0
IPT 64GT/S UCIE-A PHY
The UCIe-A_HS 64Gbps Die-to-Die (D2D) PHY IP is a cutting-edge solution designed to meet the growing demand for ultra-high-speed interconnects between...