2201 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 9 tracks, UMC 40nm LP process UMC 40nm LP/HVT Logic process 9-Track Standard Cell Library (POWERSLASH Core)....

2202 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm LL process UMC 65nm LL/HVT Low-K Logic process POWERSLASH Core Cell Library....

2203 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm SP process UMC 65nm SP/HVT process POWERSLASH Cell Library....

2204 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm LL process UMC 90nm LL/HVT Low-K Logic process Cell Library POWERSLASH Core Cell Library (high density Version)....

2205 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm SP process UMC 90nm SP/HVT Low-K process POWERSLASH Core Cell Library libary....

2206 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 28nm HLP process UMC 28nm Logic and Mixed-Mode HLP/LVT process 12-Track POWERSLASH Cell Library (C35)....

2207 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 40nm LP process UMC 40nm LP/LVT Logic process 12-Track high speed POWERSLASH Core Cell Library....

2208 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 55nm LP process UMC 55nm LP/LVT Low-K Logic process 12-Track POWERSLASH Core Cell Library....

2209 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Generic Core Cell Library wtih LPLUS (C38)....

2210 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library....

2211 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LMINUS (C30)....

2212 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HPC process UMC 28nm HPC/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library (C35)....

2213 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 40nm LP process UMC 40nm LP/LVT Low-K Logic process 7-Track POWERSLASH Cell Library....

2214 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 55nm LP process UMC 55nm LP/LVT Low-K Logic process 7-Track POWERSLASH Core Cell Library....

2215 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 8 tracks, UMC 55nm LP process UMC 55nm LP/LVT Low-K Logic process 8-Track POWERSLASH Core Cell Library....

2216 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 9 tracks, UMC 28nm HLP process UMC 28nm HLP/LVT Logic process 9-Track POWERSLASH standard Core Cell Library (C35)....

2217 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 9 tracks, UMC 40nm LP process UMC 40nm LP/LVT Logic process 9-Track Standard Cell Library (POWERSLASH Core)....

2218 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 28nm HLP process UMC 28nm Logic and Mixed-Mode HLP/RVT process 12-Track Standard POWERSLASH Core Cell Library (C35)....

2219 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 40nm LP process UMC 40nm LP/RVT Logic process 12-Track high speed POWERSLASH Cell Library (C40)....

2220 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 55nm LP process UMC 55nm LP/RVT Low-K Logic process 12-Track POWERSLASH Core Cell Library....

2221 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library....

2222 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LMINUS (C30 RVT)....

2223 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LPLUS (C38)....

2224 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HPC process UMC 28nm HPC/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library (C35)....

2225 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 40nm LP process UMC 40nm LP/RVT Low-K Logic process 7-Track POWERSLASH Cell Library....

2226 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm LP process UMC 55nm LP/RVT Low-K Logic process 7-Track POWERSLASH Core Cell Library....

2227 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm SP process UMC 55nm SP/RVT Logic process 7-Track POWERSLASH Cell Library....

2228 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 8 tracks, UMC 55nm LP process UMC 55nm LP/RVT Low-K Logic process 8-Track POWERSLASH Core Cell Library....

2229 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 9 tracks, UMC 28nm HLP process UMC 28nm Logic and Mixed-Mode HLP/RVT process 9-Track POWERSLASH Cell Library (C35)....

2230 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 9 tracks, UMC 40nm LP process UMC 40nm LP/RVT Logic process 9-Track Standard Cell Library (POWERSLASH Core)....

2231 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process UMC 55nm SP/RVT Low-K Logic process UHS Library POWERSLASH cells....

2232 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process UMC 55nm SP/RVT Low-K Logic process Powerlash Core Cell Library....

2233 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm LL process UMC 65nm LL/RVT Low-K process Mini-Library POWERSLASHKit....

2234 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm SP process UMC 65nm SP/RVT Low-K Logic process Powerlash Core Cell Library....

2235 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm LL process UMC 90nm LL/RVT Low-K process Low Power POWERSLASH Core Cell Library....

2236 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm SP process UMC 90nm SP/RVT Low-K process Low Power standard Cell Library....

2237 0.118

Standard Cell PowerSlash(TM) Library IP, UMC 0.11um LL/FSG process UMC 0.11um LL/FSG Logic process high density POWERSLASH Core Cell Library....

2238 0.118

Standard Cell PowerSlash(TM) Library IP, UMC 0.13um HS/FSG process UMC 0.13um HS/FSG process FSC0H_J POWERSLASHKit core Library....

2239 0.118

Standard Cell PowerSlash(TM) Library IP, UMC 0.13um LL/FSG process UMC 0.13um LL FSG Logic process high density POWERSLASH Core Cell Library....

2240 0.118

Standard Cell PowerSlash(TM) Library IP, UMC 0.13um SP/FSG process UMC 0.13um SP FSG Logic process high density POWERSLASH Core Cell Library....

2241 0.118

Ethernet MAC IP, 10/100 Ethernet MAC, Soft IP 10/100 Ethernet MAC with MII or RMII (Reduced MII) interface....

2242 0.118

Ethernet MAC IP, 10/100/1G Ethernet MAC, DMA (Direct Memory Access) function embedded, Soft IP 10/100/1000 Ethernet Controller with AHB bus....

2243 0.118

FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer rate. This IP is compliant with the V-By-One HS Standard, Ver. 1.3. It transfers the packed packet from direct the video stream FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer rate. This IP is compli...

2244 0.118

Dual Port SRAM Compiler IP, High density, (2RW), UMC 0.13um HS/FSG process UMC 0.13um HS/FSG Logic process high density synchronous Dual Port (2RW) SRAM memory compiler....

2245 0.118

Dual Port SRAM Compiler IP, Output: 1.8432MHz, UMC 40nm LP process UMC 40nm LP Logic process synchronous high density Dual Port SRAM memory compiler....

2246 0.118

Dual Port SRAM Compiler IP, Support Repair Features, UMC 40nm LP process UMC 40nm Logic process synchronous high density Dual Port SRAM memory compiler with redundancy....

2247 0.118

Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm eHV process UMC 55nm eHV process, Dual Port SRAM compiler with row redundancy option....

2248 0.118

Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm LP process UMC 55nm LP Logic process Synchronous Dual Port SRAM with redundancy feature....

2249 0.118

Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process UMC 55nm 1.0V Standard Performance (SP) Low-K Logic process synchronous, high density, Dual Port SRAM with row redundancy option....

2250 0.118

Dual Port SRAM Compiler IP, Support Repair Features, UMC 55nm SP process UMC 55nm SP Low-K Logic process Low Power synchronous high density Dual Port SRAM memory compiler with redundancy....