Design & Reuse
5423 IP
2001
1.0
TSMC CLN40G 40nm General Purpose PLL - 340MHz-1700MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
2002
1.0
TSMC CLN40G 40nm Multi Phase DLL - 170MHz-850MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2003
1.0
TSMC CLN40G 40nm Multi Phase DLL - 340MHz-1700MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2004
1.0
TSMC CLN40G 40nm Multi Phase DLL - 680MHz-3400MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2005
1.0
TSMC CLN40G 40nm Spread Spectrum PLL - 150MHz-750MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2006
1.0
TSMC CLN40G 40nm Spread Spectrum PLL - 300MHz-1500MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2007
1.0
TSMC CLN40G 40nm Spread Spectrum PLL - 600MHz-3000MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2008
1.0
TSMC CLN40LP 40nm Clock Generator PLL - 150MHz-750MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2009
1.0
TSMC CLN40LP 40nm Clock Generator PLL - 300MHz-1500MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2010
1.0
TSMC CLN40LP 40nm Clock Generator PLL - 75MHz-375MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2011
1.0
TSMC CLN40LP 40nm DDR DLL - 112MHz-560MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2012
1.0
TSMC CLN40LP 40nm DDR DLL - 177MHz-885MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2013
1.0
TSMC CLN40LP 40nm DDR DLL - 84MHz-420MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2014
1.0
TSMC CLN40LP 40nm Deskew PLL - 150MHz-750MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2015
1.0
TSMC CLN40LP 40nm Deskew PLL - 300MHz-1500MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2016
1.0
TSMC CLN40LP 40nm Deskew PLL - 75MHz-375MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2017
1.0
TSMC CLN40LP 40nm General Purpose PLL - 150MHz-750MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
2018
1.0
TSMC CLN40LP 40nm Multi Phase DLL - 150MHz-750MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2019
1.0
TSMC CLN40LP 40nm Multi Phase DLL - 300MHz-1500MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2020
1.0
TSMC CLN40LP 40nm Multi Phase DLL - 75MHz-375MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2021
1.0
TSMC CLN40LP 40nm Spread Spectrum PLL - 150MHz-750MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2022
1.0
TSMC CLN40LP 40nm Spread Spectrum PLL - 300MHz-1500MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2023
1.0
TSMC CLN40LP 40nm Spread Spectrum PLL - 75MHz-375MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2024
1.0
TSMC CLN55GP 55nm Clock Generator PLL - 130MHz-650MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2025
1.0
TSMC CLN55GP 55nm Clock Generator PLL - 260MHz-1300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2026
1.0
TSMC CLN55GP 55nm Clock Generator PLL - 520MHz-2600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2027
1.0
TSMC CLN55GP 55nm DDR DLL - 150MHz-750MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2028
1.0
TSMC CLN55GP 55nm DDR DLL - 200MHz-1000MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2029
1.0
TSMC CLN55GP 55nm DDR DLL - 316MHz-1580MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2030
1.0
TSMC CLN55GP 55nm Deskew PLL - 130MHz-650MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2031
1.0
TSMC CLN55GP 55nm Deskew PLL - 260MHz-1300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2032
1.0
TSMC CLN55GP 55nm Deskew PLL - 520MHz-2600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2033
1.0
TSMC CLN55GP 55nm General Purpose PLL - 260MHz-1300MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
2034
1.0
TSMC CLN55GP 55nm Multi Phase DLL - 130MHz-650MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2035
1.0
TSMC CLN55GP 55nm Multi Phase DLL - 260MHz-1300MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2036
1.0
TSMC CLN55GP 55nm Multi Phase DLL - 520MHz-2600MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....
2037
1.0
TSMC CLN55GP 55nm Spread Spectrum PLL - 130MHz-650MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2038
1.0
TSMC CLN55GP 55nm Spread Spectrum PLL - 260MHz-1300MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2039
1.0
TSMC CLN55GP 55nm Spread Spectrum PLL - 520MHz-2600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
2040
1.0
TSMC CLN55LP 55nm Clock Generator PLL - 120MHz-600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2041
1.0
TSMC CLN55LP 55nm Clock Generator PLL - 240MHz-1200MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2042
1.0
TSMC CLN55LP 55nm Clock Generator PLL - 60MHz-300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
2043
1.0
TSMC CLN55LP 55nm DDR DLL - 104MHz-520MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2044
1.0
TSMC CLN55LP 55nm DDR DLL - 164MHz-820MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2045
1.0
TSMC CLN55LP 55nm DDR DLL - 78MHz-390MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
2046
1.0
TSMC CLN55LP 55nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2047
1.0
TSMC CLN55LP 55nm Deskew PLL - 240MHz-1200MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2048
1.0
TSMC CLN55LP 55nm Deskew PLL - 60MHz-300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
2049
1.0
TSMC CLN55LP 55nm General Purpose PLL - 120MHz-600MHz
The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...
2050
1.0
TSMC CLN55LP 55nm Multi Phase DLL - 120MHz-600MHz
The Multi Phase DLL is designed for high-speed interface applications. The DLL generates precise multi-phase clocks directly from the reference clock....