Atria Logic, Inc. IP Cores

You must be registered with the D&R website to view the full search results, including:

Complete datasheets for Atria Logic, Inc. IP Core products
Contact information for Atria Logic, Inc. IP Core suppliers

Please log in here to your account.

New user ? Signup here.

551

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60) w/ Forward Bias. W/ deep Nwell....

552

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60). W/O deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60). W/O deep Nwell...

553

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

554

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90). W/O deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90). W/O deep Nwell....

555

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60) w/ Forward Bias. W/ deep Nwell....

556

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60). W/O deep Nwell...

557

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell...

558

0.118

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell.

UMC 55nm ULP/HVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90).W/O deep Nwell....

559

0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell...

560

0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60)

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60)...

561

0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell.

UMC 55nm ULP/LVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60).W/O deep Nwell....

562

0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...

563

0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)...

564

0.118

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)

UMC 55nm ULP/LVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)...

565

0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell.

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C60). W/O deep Nwell....

566

0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60). W/O deep Nwell

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Generic Core Cell Library (C60). W/O deep Nwell...

567

0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell.

UMC 55nm ULP/RVT Low-K Logic Process Process 6-track Powerslash Cell Library (C60). W/O deep Nwell....

568

0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C60)...

569

0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Generic Core Cell Library (C60)...

570

0.118

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)

UMC 55nm ULP/RVT Low-K Logic Process Process 8-track Powerslash Cell Library (C60)...

571

0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

572

0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Generic Core Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

573

0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/uHVT Low-K Logic Process Process 6-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

574

0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track ECO M1 Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

575

0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Generic Core Cell Library (C90) w/ Forward Bias...

576

0.118

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell.

UMC 55nm ULP/uHVT Low-K Logic Process Process 8-track Powerslash Cell Library (C90) w/ Forward Bias. W/ deep Nwell....

577

0.118

UMC 55nm uLP/uHVT LowK Logic Process Ultra High Density (6T) Generic Core Cell Library

UMC 55nm uLP/uHVT LowK Logic Process Ultra High Density (6T) Generic Core Cell Library...

578

0.118

UMC 65nm LL Lowk Logic Process 1.8V I2C IO for Sony

UMC 65nm LL Lowk Logic Process 1.8V I2C IO for Sony...

579

0.118

UMC 65nm LL/RVT 1P10M LowK Logic Process 1.8V/3.3V multi-voltage generic I/O cell library

UMC 65nm LL/RVT 1P10M LowK Logic Process 1.8V/3.3V multi-voltage generic I/O cell library...

580

0.118

UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler.

UMC 65nm SP LowK Logic Process synchronous single port register file SRAM memory compiler....

581

0.118

UMC 65nm SP/RVT Logic Process MPCA cell library

UMC 65nm SP/RVT Logic Process MPCA cell library...

582

0.118

UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC BOAC Pad

UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC BOAC Pad...

583

0.118

UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC pad

UMC 90nm LL/RVT Low-K Logic Process 2.5VOD3.3V Low Frequency OSC pad...

584

0.118

UMC 90nm SP-HVT LowK Logic Process High Speed PowerSlash Kit

UMC 90nm SP-HVT LowK Logic Process High Speed PowerSlash Kit...

585

0.118

UMC 90nm SP-RVT LowK Logic Process High Speed PowerSlash Kit

UMC 90nm SP-RVT LowK Logic Process High Speed PowerSlash Kit...

586

0.118

UMC 90nm SP/RVT LowK Logic Process ECO M1 core cell library

UMC 90nm SP/RVT LowK Logic Process ECO M1 core cell library...

587

0.118

UMC 90nm Standard Performance LowK Logic Process Synchronous high density single port register file SRAM memory compiler

UMC 90nm Standard Performance LowK Logic Process Synchronous high density single port register file SRAM memory compiler...

588

0.118

An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process

An 8-bit 10MSPS Programmable Gain Amplifier ;UMC 55nm SP-HVT LowK Logic Process...

589

0.118

An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process.

An ADDLL operate at 50MHz~210MHz. Supports slave delay line to generate per 1/32 UI programmable delay UMC 40nm LP/RVT Logic Process....

590

0.118

Analog Comparator; 0.25um Logic process

Analog Comparator; 0.25um Logic process...

591

0.118

Analog part of 600Mbps to 4Gbps 8-lane V-By-One transmitter with embedded PLL circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process.

Analog part of 600Mbps to 4Gbps 8-lane V-By-One transmitter with embedded PLL circuit, VCC=0.9V; UMC 28nm HPC+ LowK Logic Process....

592

0.118

ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process

ONFI PHY Compensation Block for ONFI4.0 application; UMC 40nm LP/RVT Logic Process...

593

0.118

Input VCC3V=3.3V, 3.3V Power On Reset; UMC 40nm LP Logic Process

Input VCC3V=3.3V, 3.3V Power On Reset; UMC 40nm LP Logic Process...

594

0.118

Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process_x005F_x005F_x005F_x000D_ _x005F_x005F_x005F_x000D_

Input 1.2V, VBG=0.8V BandGap; UMC 65nm LL/RVT LowK Logic Process...

595

0.118

Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL; UMC 0.11um EFLASH logic process

Input 10-200MHz, output 25-400MHz, frequency synthesizable PLL; UMC 0.11um EFLASH logic process...

596

0.118

Input 10M-200M Hz, output 20M-400M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT Low-K Logic Process

Input 10M-200M Hz, output 20M-400M Hz, frequency synthesizable PLL; UMC 55nm LP/RVT Low-K Logic Process...

597

0.118

Input 10M-70MHz, output 10M-70MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF. UMC 40nm LP Logic Process

Input 10M-70MHz, output 10M-70MHz. An all digital slave delay line of FXADDLL070HH0L to generate pulse-width tunabble clock in period of FREF. UMC 40n...

598

0.118

Input 12M Hz, output 40M-850M Hz, frequency synthesizable PLL; UMC 28nm HPC Logic Process

Input 12M Hz, output 40M-850M Hz, frequency synthesizable PLL; UMC 28nm HPC Logic Process...

599

0.118

Input 12MHz, output 900 MHz/1200MHz, 600 MHz/800 MHz, 360 MHz/480MHz, 300 MHz/400MHz, frequency synthesizable PLL; UMC 55nm SP/RVT LowK Logic Process

Input 12MHz, output 900 MHz/1200MHz, 600 MHz/800 MHz, 360 MHz/480MHz, 300 MHz/400MHz, frequency synthesizable PLL; UMC 55nm SP/RVT LowK Logic Process...

600

0.118

Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm eflash LP/RVT Logic Process

Input 2.0V-3.6V, VBG=1.2V Band-gap, UMC 55nm eflash LP/RVT Logic Process...

13|

14|

...|