Design & Reuse
6106 IP
951
50.0
PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, N7, N3P, N2P)
The multi-channel Synopsys PHY IP for PCI Express® 4.0 includes Synopsys’ high-speed, high-performance transceiver to meet today’s applications’ deman...
952
50.0
PCIe 5.0 PHY in TSMC (16nm, 12nm, N7, N6, N6C, N5, N4P, N4C, N3E, N3P, N2P)
The multi-channel Synopsys PHY IP for PCI Express® 5.0 and CXL includes Synopsys’ high-speed, high-performance transceiver to meet today’s applicatio...
953
50.0
PCIe Gen3 to SRIO Gen3 Bridge (FPGA)
Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Expre...
954
50.0
PCIe Gen5 NVMe SSD RAMDISK Reference Platform
Mobiveil’s RAMDISK-Gen5is a PCIe Gen5 and 1.4 NVMe compliant Ramdisk that emulates the next generation NVMe Gen5 SSDs with high performance. With hi...
955
50.0
SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller
Arasan Chip Systems’ eMMC 5.0 / SD3.0 Host Controller IP (3MCR) is a highly integrated host controller IP solution that supports three key memory and ...
956
50.0
HDMI 2.1 Tx PHY in TSMC (16nm, 12nm, N7, N6, N6C, N4, N3E)
The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...
957
50.0
HDMI 2.1/DisplayPort 2.1 TX PHY in TSMC (N3E, N3P)
The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...
958
50.0
DDR5 PHY in TSMC (N5, N4P, N3P, N3E)
The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...
959
50.0
Ceva-Waves Bluetooth 5.4 dual mode Baseband Controller
Ceva-Waves Bluetooth 5.4 dual mode IP is a complete and flexible solution for integration into SoCs/ASSPs. It contains both "classic" BR/EDR Bluetoot...
960
50.0
Ceva-Waves Bluetooth 6.0 dual mode Baseband Controller
Ceva-Waves Bluetooth dual mode IP is a complete and flexible solution for integration into SoCs/ASSPs. It has been qualified for Bluetooth Core Specif...
961
50.0
UFS 4.0 Host Controller compatible with M-PHY 5.0 and UniPro 2.0
The Arasan UFS Host -UniPro IP is a simple, high performance, serial interface used primarily in mobile systems between host processing and NVM mass s...
962
50.0
5G Baseband Platform IP for Mobile Broadband and IoT
PentaG2™ is Ceva’s second generation 5G NR baseband modem IP platform. It is the industry’s only platform offering capable of meeting the extreme perf...
963
50.0
AHB Octal SPI Controller with PSRAM and XIP Support
The Silvaco Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, usually an ind...
964
50.0
High Performance DDR5/4/3 Memory Controller
Mobiveil's DDR5/4/3 Memory Controller is a highly flexible and configurable design targeted for high performance enterprise server and real-time consu...
965
50.0
MIPI C-PHY v1.0 D-PHY v1.2 TX 2 trios/2 Lanes in TSMC (12nm, N5, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
966
50.0
MIPI C-PHY v1.0 D-PHY v1.2 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
967
50.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N4, N4P, N3E, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
968
50.0
MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N7, N6, N5, N4, N4C, N3E, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
969
50.0
MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N6, N6C, N5, N4P, N4C, N3)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
970
50.0
MIPI D-PHY Universal Tx / Rx v1.1 @1.5ghz Ultra Low Power for IoT & Wearables
Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on TSMC 22nm process technology for SoC designs. Arasan’s D-PHY IP is ava...
971
50.0
MIPI DSI-2 Receiver Controller v1.0
The Arasan DSI-2 Device Controller IP is designed to provide MIPI DSI-2 1.0 compliant high speed serial connectivity for mobile display modules with T...
972
50.0
MIPI M-PHY - TSMC 40nm
MIPI M-PHY Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY config...
973
50.0
MIPI M-PHY G4 Type 1 2Tx2RX in TSMC (16nm, 12nm, N7, N6, N5, N4, N3A, N3E)
The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v5.0 specification, supports speeds up to 23.32 Gbps per lane. The I...
974
50.0
Ultra High-Speed Cache Memory Compiler
Silvaco’s Ultra High-Speed cache memory is an adaptable, independent, non-coherent cache Intellectual Property (IP) featuring an advanced cache ar...
975
50.0
ONFI 3.2 NV-DDR2 PHY in GDSII
Compliant to ONFI 3.2 electrical interface, Arasan ONFI 3.2 PHY, delivered in hard macro, is process technology proven and easy to integrate. This ON...
976
50.0
ONFI 4.0 NAND Flash Controller & PHY
The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP is changing with it. New applications are emerging and innovative IP solu...
977
50.0
ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP Core is changing in accordance with it. New applications are emerging and...
978
50.0
ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP Core is changing in accordance with it. New applications are emerging and...
979
50.0
Modern, high performance Audio DSP, optimized for far-field noise reduction and Artificial Intelligence speech recognition
The Ceva-BX2 audio/voice DSP is targeted for high performance audio devices such as DTV, Smart Speaker, Soundbar, and car infotainment systems. Ceva-...
980
50.0
LPDDR5/4x/4 combo PHY on 14nm, 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
981
50.0
LPDDR5X/5/4X PHY in TSMC (N5, N4P, N4C, N3E, N3P, N3A)
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...
982
50.0
Open RAN Platform for Base Station and Radio
Industry’s First Comprehensive 5G Baseband Platform IP for 5G RAN ASICs and Open RAN Building on more than a decade of leadership in baseband IP solut...
983
50.0
USB 2.0 nanoPHY in SMIC (65nm)
The Synopsys USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low-power mobile and consumer applicati...
984
50.0
USB 3.1 PHY (10G/5G) inTSMC (16nm, 12nm, N7, N6, N5,N3E, N3P)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...
985
50.0
USB-C 3.1 DP/TX PHY ebdaux in TSMC (N5, N4P, N4C, N3E)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...
986
50.0
USB-C 3.2 DP/TX PHY in TSMC (N3E)
The Synopsys USB-C 3.2/DisplayPort 1.4 IP solution consists of USB-C 3.2/DisplayPort 1.4 PHYs, USB-C 3.2/DisplayPort 1.4 controllers (Device, Host, or...
987
50.0
USB-C 3.2 SS/SSP PHY in Type-C in TSMC (N7, N6, N5, N3E)
The Synopsys SuperSpeed 3.2 USB IP solution is based on the USB 3.2 specification from the USB Implementer Forum. The USB 3.2 IP offering includes con...
988
50.0
TSMC 3nm (N3E) 1.2V LVDS
Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...
989
50.0
TSMC 3nm (N3E) 1.2V/1.8V GPIO Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
990
50.0
TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
991
50.0
TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries, multiple metalstacks
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
992
50.0
TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries
Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...
993
50.0
TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries, multiple metalstacks
Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...
994
50.0
TSMC 3nm (N3E) 1.5V LVDS
Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...
995
50.0
TSMC 3nm (N3E) 1.8V SD/eMMC IO
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...
996
50.0
TSMC 3nm (N3E) 1.8V SD/eMMC PHY
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...
997
50.0
TSMC 3nm (N3E) 1.8V SD/eMMC PHY, multiple metalstacks
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...
998
50.0
TSMC 3nm (N3E) GPIO Basekit Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
999
50.0
Quad SPI Controller
The Serial Peripheral Interface or SPI-bus is a simple 4- wire serial communications interface used by many peripheral chips that enable the controlle...
1000
50.0
Multi-protocol wireless plaform integrating 802.11ax (Wi-Fi 6), Bluetooth 5.4 Dual Mode, 802.15.4 (for Thread, Zigbee and Matter)
Ceva-Waves Links is a versatile family of multi-protocol wireless platform IPs, encompassing the latest consumer wireless standards. It leverages the ...