Atria Logic, Inc. IP Cores

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151

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3.3v to 1.2v/1ma with power switch function ,UMC 28nm HPC Logic process

3.3v to 1.2v/1ma with power switch function ,UMC 28nm HPC Logic process...

152

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3.3V to 1.8V/150mA REG with external Capacitor, UMC 28nm HPC Logic and Mixed-Mode Process

3.3V to 1.8V/150mA REG with external Capacitor, UMC 28nm HPC Logic and Mixed-Mode Process...

153

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3.3V to 1.8V/50mA REG with external Capacitor, UMC 28nm HPC Logic and Mixed-Mode Process

3.3V to 1.8V/50mA REG with external Capacitor, UMC 28nm HPC Logic and Mixed-Mode Process...

154

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3.3V to 1.8V/50mA REG with external Capacitor, UMC 28nm HPC Logic and Mixed-Mode Process

3.3V to 1.8V/50mA REG with external Capacitor, UMC 28nm HPC Logic and Mixed-Mode Process...

155

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3.3V to 2.0V with 288mA driving capability with external capacitor,use trimming ports (need e-Fuse IP); Linear Regulator; UMC 28nm Logic HPC Process

3.3V to 2.0V with 288mA driving capability with external capacitor,use trimming ports (need e-Fuse IP); Linear Regulator; UMC 28nm Logic HPC Process...

156

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3.3V to 2.5V Regulator with 150mA; UMC 40nm LP/RVT LowK Logic Process

3.3V to 2.5V Regulator with 150mA; UMC 40nm LP/RVT LowK Logic Process...

157

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3.3V to 2.5V with 100mA driving capability; Linear Regulator ; MIFS C40LP Logic Process

3.3V to 2.5V with 100mA driving capability; Linear Regulator ; MIFS C40LP Logic Process...

158

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3.3v to 2.5v with 30mA driving capability without external capacitor (Cap-less), use trimming PADs; Linear Regulator; UMC 40nm LP/RVT LowK Logic process

3.3v to 2.5v with 30mA driving capability without external capacitor (Cap-less), use trimming PADs; Linear Regulator; UMC 40nm LP/RVT LowK Logic proce...

159

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3.3V to 2.5V with 5mA driving capability; Capacitor-free Linear Regulator; UMC 0.11um HS/AE Logic Process

3.3V to 2.5V with 5mA driving capability; Capacitor-free Linear Regulator; UMC 0.11um HS/AE Logic Process...

160

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3.3v to 2.5v/5mA , REG, Linear Regulator, UMC 55nm LP/RVT Logic Process

3.3v to 2.5v/5mA , REG, Linear Regulator, UMC 55nm LP/RVT Logic Process...

161

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1.4V~3.6V to 1.2V with 100mA driving capability; Linear Regulator; UMC 90nm LL/RVT LowK LOGIC PROCESS minLib Cell Library

1.4V~3.6V to 1.2V with 100mA driving capability; Linear Regulator; UMC 90nm LL/RVT LowK LOGIC PROCESS minLib Cell Library...

162

0.118

2.5V LVDS Transmitter 1.25Gbps; UMC 40nm LP LowK Logic Process.

2.5V LVDS Transmitter 1.25Gbps; UMC 40nm LP LowK Logic Process....

163

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2.5V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process. (Modify layout )

2.5V LVDS Transmitter 700Mbps; UMC 40nm LP LowK Logic Process. (Modify layout )...

164

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2.7V~3.3V to 1.8V with 150mA driving capability; Linear Regulator; UMC 55nm LP/RVT LowK Logic Process

2.7V~3.3V to 1.8V with 150mA driving capability; Linear Regulator; UMC 55nm LP/RVT LowK Logic Process...

165

0.118

1.7V~3.6V to 1.0V with 600mA driving capability, Linear Regulator,UMC 55nm LP/RVT LowK Logic Process

1.7V~3.6V to 1.0V with 600mA driving capability, Linear Regulator,UMC 55nm LP/RVT LowK Logic Process...

166

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1.8V 10bit 80MSPS Dual-Channel Pipelined ADC; UMC 0.153um Logic Process_x005F_x005F_x005F_x000D_

1.8V 10bit 80MSPS Dual-Channel Pipelined ADC; UMC 0.153um Logic Process...

167

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1.8V 10bit 80MSPS Pipelined ADC; UMC 0.153um Logic Process

1.8V 10bit 80MSPS Pipelined ADC; UMC 0.153um Logic Process...

168

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1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process

1.8v LVDS RX IO 800Mbps, UMC 40nm LP/RVT LowK Logic Process...

169

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0.9V/1.8V 9Bits 125MSPS Pipelined ADC; UMC 28nm HPC+, LowK, Logic Process

0.9V/1.8V 9Bits 125MSPS Pipelined ADC; UMC 28nm HPC+, LowK, Logic Process...

170

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D/A Converter IP, 10 bits, 1MHz, UMC 0.153um Logic process

10-Bit 1MHz Voltage Output R-2R Digital-to-Analog converter, UMC 0.153um Logic process....

171

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D/A Converter IP, 10 bits, 2.5Msps, HJTC 0.18um Logic process

10-Bit 2.5MSPS current Digital-to-Analog converter, HJ 0.18um Logic process....

172

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D/A Converter IP, 16 bits, 96Ksps, UMC 0.25um Logic process

16-Bit 96KSPS voltage output stereo-line Digital-to-Analog converter, UMC 0.25um Logic process....

173

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A/D Converter IP, 10 bits, 300Ksps, UMC 0.35um Logic process

10-Bit 300KSPS single End Analog-to-Digital converter, UMC 0.35um Logic process....

174

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A/D Converter IP, 10 bits, 30Msps, UMC 0.25um Logic process

10-Bit 30MSPS Differential Analog-to-Digital converter, UMC 0.25um Logic process....

175

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A/D Converter IP, 10 bits, 400Ksps, UMC 0.25um Logic process

10-Bit 400KSPS single-end Analog-to-Digital converter, UMC 0.25um Logic process....

176

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A/D Converter IP, 18 bits, 96Ksps, UMC 0.25um Logic process

18-Bit 96KSPS differential Sigma-Delta Analog-to-Digital converter, UMC 0.25um Logic process....

177

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10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process

10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process...

178

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10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process

10 bit 1MSPS A/D Converter; UMC 40 nm LP/RVT Low-K Logic Process...

179

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10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process

10 lane FXSLVTX030HH0L bias circuit ; UMC 40nm LP/RVT Logic Process...

180

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10bit 250MSPS Current-steering Video D/A Converter; UMC 0.11um HS/FSG Logic Process

10bit 250MSPS Current-steering Video D/A Converter; UMC 0.11um HS/FSG Logic Process...

181

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40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process

40nm LPDDR3-PHY Data block for LightCo ; UMC 40nm LP/LVT Logic Process...

182

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12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.13um LL/RVT FSG Logic Process

12bit 1MSPS SAR ADC with 8-1 Mux (All C-type) ; UMC 0.13um LL/RVT FSG Logic Process...

183

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28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process

28Gb/s 4 lane high-speed SerDes; UMC 28nm HPC Logic Std/HS process...

184

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28nm Logic and Mixed-Mode HLP/RVT Process Multi-Voltage BOAC I/O Cell library

28nm Logic and Mixed-Mode HLP/RVT Process Multi-Voltage BOAC I/O Cell library...

185

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28nm Logic and Mixed-Mode HPC/RVT Process Multi-Voltage BOAC I/O Cell library

28nm Logic and Mixed-Mode HPC/RVT Process Multi-Voltage BOAC I/O Cell library...

186

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1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process

1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process...

187

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1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process

1:2 DDR2/DDR1/MDDR combo PHY; UMC 0.11um HS/Cu Logic Process...

188

0.118

Band Gap IP, Input: 1.2V - 1.98V, VBG=0.615V, UMC 0.153um Logic process

Input 1.2V-1.98V, VBG=0.615V bandgap, UMC 0.153um Logic process....

189

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Band Gap IP, Input: 2.0V - 3.3V, VBG=1.23V, UMC 0.25um Logic process

VBG=1.23V, VCCAH=3.3V, VCCAH_min=2.0V, Ivccah=25uA, UMC 0.25um Logic process....

190

0.118

Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process

Data block of 1:2 DDR2-PHY ; UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process...

191

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Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process

Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm LP/RVT LowK Logic Process...

192

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Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process

Data Block of DDR3 Combo PHY for DIMM version ; UMC 55nm SP/RVT LowK Logic Process...

193

0.118

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant to DFI); UMC 55nm SP/RVT LowK Logic Process...

194

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Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application (compliant with DFI spec); UMC 40nm LP LowK Logic Process...

195

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Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...

196

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Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm LP/RVT LowK Logic Process...

197

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Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...

198

0.118

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process

Data Block of DDR3/DDR3L/DDR2/LPDDR2/LPDDR Combo PHY for Chip Application; UMC 55nm SP/RVT LowK Logic Process...

199

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Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for copper pillar bump Flip chip version ; UMC 40nm LP LowK Logic Process...

200

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Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process

Data Block of DDR3/DDR4/LPDDR2/LPDDR3 Combo PHY for Solder bump Flip chip version ; UMC 40nm LP LowK Logic Process...

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