Atria Logic, Inc. IP Cores

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2601

1.0

TSMC CL015LV 150nm Deskew PLL - 280MHz-1400MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2602

1.0

TSMC CL015LV 150nm Deskew PLL - 70MHz-350MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2603

1.0

TSMC CL015LV 150nm Spread Spectrum PLL - 140MHz-700MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2604

1.0

TSMC CL015LV 150nm Spread Spectrum PLL - 280MHz-1400MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2605

1.0

TSMC CL015LV 150nm Spread Spectrum PLL - 70MHz-350MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2606

1.0

TSMC CL018E 180nm Clock Generator PLL - 130MHz-650MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2607

1.0

TSMC CL018E 180nm Clock Generator PLL - 260MHz-1300MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2608

1.0

TSMC CL018E 180nm Clock Generator PLL - 65MHz-325MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2609

1.0

TSMC CL018E 180nm DDR DLL - 120MHz-600MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2610

1.0

TSMC CL018E 180nm DDR DLL - 57MHz-285MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2611

1.0

TSMC CL018E 180nm DDR DLL - 76MHz-380MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2612

1.0

TSMC CL018E 180nm Deskew PLL - 130MHz-650MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2613

1.0

TSMC CL018E 180nm Deskew PLL - 260MHz-1300MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2614

1.0

TSMC CL018E 180nm Deskew PLL - 65MHz-325MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2615

1.0

TSMC CL018E 180nm Spread Spectrum PLL - 130MHz-650MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2616

1.0

TSMC CL018E 180nm Spread Spectrum PLL - 260MHz-1300MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2617

1.0

TSMC CL018E 180nm Spread Spectrum PLL - 65MHz-325MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2618

1.0

TSMC CL018G 180nm Clock Generator PLL - 110MHz-550MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2619

1.0

TSMC CL018G 180nm Clock Generator PLL - 220MHz-1100MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2620

1.0

TSMC CL018G 180nm Clock Generator PLL - 55MHz-275MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2621

1.0

TSMC CL018G 180nm DDR DLL - 42MHz-210MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2622

1.0

TSMC CL018G 180nm DDR DLL - 56MHz-280MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2623

1.0

TSMC CL018G 180nm DDR DLL - 88MHz-440MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2624

1.0

TSMC CL018G 180nm Deskew PLL - 110MHz-550MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2625

1.0

TSMC CL018G 180nm Deskew PLL - 220MHz-1100MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2626

1.0

TSMC CL018G 180nm Deskew PLL - 55MHz-275MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2627

1.0

TSMC CL018G 180nm Spread Spectrum PLL - 110MHz-550MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2628

1.0

TSMC CL018G 180nm Spread Spectrum PLL - 220MHz-1100MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2629

1.0

TSMC CL018G 180nm Spread Spectrum PLL - 55MHz-275MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2630

1.0

TSMC CL018LP 180nm Clock Generator PLL - 180MHz-900MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2631

1.0

TSMC CL018LP 180nm Clock Generator PLL - 45MHz-225MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2632

1.0

TSMC CL018LP 180nm Clock Generator PLL - 90MHz-450MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2633

1.0

TSMC CL018LP 180nm DDR DLL - 30MHz-150MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2634

1.0

TSMC CL018LP 180nm DDR DLL - 40MHz-200MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2635

1.0

TSMC CL018LP 180nm DDR DLL - 63MHz-315MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2636

1.0

TSMC CL018LP 180nm Deskew PLL - 180MHz-900MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2637

1.0

TSMC CL018LP 180nm Deskew PLL - 45MHz-225MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2638

1.0

TSMC CL018LP 180nm Deskew PLL - 90MHz-450MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2639

1.0

TSMC CL018LP 180nm Spread Spectrum PLL - 180MHz-900MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2640

1.0

TSMC CL018LP 180nm Spread Spectrum PLL - 45MHz-225MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2641

1.0

TSMC CL018LP 180nm Spread Spectrum PLL - 90MHz-450MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

2642

1.0

TSMC CL018LV 180nm Clock Generator PLL - 118MHz-590MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2643

1.0

TSMC CL018LV 180nm Clock Generator PLL - 236MHz-1180MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2644

1.0

TSMC CL018LV 180nm Clock Generator PLL - 59MHz-295MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

2645

1.0

TSMC CL018LV 180nm DDR DLL - 101MHz-505MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2646

1.0

TSMC CL018LV 180nm DDR DLL - 48MHz-240MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2647

1.0

TSMC CL018LV 180nm DDR DLL - 64MHz-320MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

2648

1.0

TSMC CL018LV 180nm Deskew PLL - 118MHz-590MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2649

1.0

TSMC CL018LV 180nm Deskew PLL - 236MHz-1180MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

2650

1.0

TSMC CL018LV 180nm Deskew PLL - 59MHz-295MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

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