Atria Logic, Inc. IP Cores

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301

0.118

DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process

DLL-based cell that generates 32 phase delay for SDIO; Frequency range: 52MHz~208MHz; UMC 28nm HPC Logic Process...

302

0.118

DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process

DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process...

303

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DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process

DLL-based LVDS RX 3.3v/1.0v ; 55nm SP/RVT LowK Logic Process...

304

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DLL-based LVDS RX,VCC=3.3V for 11.5MHz ~ 34.6MHz operation frequency, UMC 0.13um HS FSG Logic Process

DLL-based LVDS RX,VCC=3.3V for 11.5MHz ~ 34.6MHz operation frequency, UMC 0.13um HS FSG Logic Process...

305

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DLL-based LVDS RX; VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation freq. 1data(581Mbps) +1clock(83Mhz). UMC 0.13um HS FSG Logic Process

DLL-based LVDS RX; VCC=3.3 for 20M~135MHz and VCC=2.5 for 20M~100MHz operation freq. 1data(581Mbps) +1clock(83Mhz). UMC 0.13um HS FSG Logic Process...

306

0.118

UMC 0.11um AE/HS logic process Multi-Voltage BOAC SD3.0 I/O Cell library

UMC 0.11um AE/HS logic process Multi-Voltage BOAC SD3.0 I/O Cell library...

307

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UMC 0.11um AL/LL Logic Process miniLib standard cell library

UMC 0.11um AL/LL Logic Process miniLib standard cell library...

308

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UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process BOAC Multi-voltage IO with Power-on Tri-state/Low Function.

UMC 0.11um HS/AE (AL Advanced Enhancement) Logic Process BOAC Multi-voltage IO with Power-on Tri-state/Low Function....

309

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UMC 0.11um HS/AL Logic Process High Density Version MPCA core cell library with mini programming layer from V1 to M4

UMC 0.11um HS/AL Logic Process High Density Version MPCA core cell library with mini programming layer from V1 to M4...

310

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UMC 0.11um HS/AL Logic Process True 3.3V Standard IO Cell Library

UMC 0.11um HS/AL Logic Process True 3.3V Standard IO Cell Library...

311

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UMC 0.11um HS/ALE Logic Process MPCA Cell Library With minimum Via1/M2/Via2/M3/Via3/M4 programming

UMC 0.11um HS/ALE Logic Process MPCA Cell Library With minimum Via1/M2/Via2/M3/Via3/M4 programming...

312

0.118

UMC 0.11um HS/FSG Logic Process high density MPCA core cell library with minimum Via1 to M4 programming

UMC 0.11um HS/FSG Logic Process high density MPCA core cell library with minimum Via1 to M4 programming...

313

0.118

UMC 0.11um LL/AE (AL Advanced Enhancement) Logic Process High-Freq0. OSC BOAC I/O.

UMC 0.11um LL/AE (AL Advanced Enhancement) Logic Process High-Freq0. OSC BOAC I/O....

314

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UMC 0.11um SP/AE (AL Advanced Enhancement) Logic Process High-Freq. OSC BOAC I/O.

UMC 0.11um SP/AE (AL Advanced Enhancement) Logic Process High-Freq. OSC BOAC I/O....

315

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UMC 0.13um HS/FSG Logic Process BOAC Multi-voltage IO with Power-on Tri-state/Low Function.

UMC 0.13um HS/FSG Logic Process BOAC Multi-voltage IO with Power-on Tri-state/Low Function....

316

0.118

UMC 0.13um HS/FSG Logic Process metal2-start programming gate array cell library for FSC0H_J (ECO_M2)

UMC 0.13um HS/FSG Logic Process metal2-start programming gate array cell library for FSC0H_J (ECO_M2)...

317

0.118

UMC 0.13um HS/FSG Logic Process Ultra-slim SSTL-2 (ClassI)/LVTTL (10mA) Combo I/O Cells

UMC 0.13um HS/FSG Logic Process Ultra-slim SSTL-2 (ClassI)/LVTTL (10mA) Combo I/O Cells...

318

0.118

UMC 0.13um LL/FSG Logic Process Metal1 Start ECO core cell library

UMC 0.13um LL/FSG Logic Process Metal1 Start ECO core cell library...

319

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UMC 0.13um LL/FSG Logic Process miniLib+ M1 ECO cells

UMC 0.13um LL/FSG Logic Process miniLib+ M1 ECO cells...

320

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UMC 0.13um SP/FSG Logic Process Metal1 Start ECO core cell library

UMC 0.13um SP/FSG Logic Process Metal1 Start ECO core cell library...

321

0.118

UMC 0.18um GII Logic Process 3.3V core cell library

UMC 0.18um GII Logic Process 3.3V core cell library...

322

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UMC 0.18um Logic GII Process true 3.3V RTC IO cell Library

UMC 0.18um Logic GII Process true 3.3V RTC IO cell Library...

323

0.118

UMC 0.25um LOGIC process standard Multi-Voltage IO

UMC 0.25um LOGIC process standard Multi-Voltage IO...

324

0.118

UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler.

UMC 0.45um Logic process standard gate array asynchronous embedded array high density two port (1R1W) SRAM memory compiler....

325

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UMC 0.45um Logic process standard gate array asynchronous high density single port SRAM memory compiler.

UMC 0.45um Logic process standard gate array asynchronous high density single port SRAM memory compiler....

326

0.118

UMC 0.45um Logic process standard gate array asynchronous metal programmed ROM memory compiler.

UMC 0.45um Logic process standard gate array asynchronous metal programmed ROM memory compiler....

327

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UMC 0.5um LOGIC process Low Voltage Gate Array true 5.0V Oscillator IO cells

UMC 0.5um LOGIC process Low Voltage Gate Array true 5.0V Oscillator IO cells...

328

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UMC 0.5um Logic process standard asynchronous high density single port SRAM memory compiler.

UMC 0.5um Logic process standard asynchronous high density single port SRAM memory compiler....

329

0.118

UMC 0.5um Logic process standard asynchronous high density two port (1R1W) SRAM memory compiler.

UMC 0.5um Logic process standard asynchronous high density two port (1R1W) SRAM memory compiler....

330

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UMC 0.5um Logic process standard asynchronous low density low power single port SRAM memory compiler.

UMC 0.5um Logic process standard asynchronous low density low power single port SRAM memory compiler....

331

0.118

UMC 0.5um Logic process standard asynchronous low density low power two port (1R1W) SRAM memory compiler.

UMC 0.5um Logic process standard asynchronous low density low power two port (1R1W) SRAM memory compiler....

332

0.118

UMC 0.5um Logic process standard asynchronous VIA2 programmed ROM memory compiler.

UMC 0.5um Logic process standard asynchronous VIA2 programmed ROM memory compiler....

333

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UMC 0.5um Logic process standard synchronous diffusion programmed ROM memory compiler.

UMC 0.5um Logic process standard synchronous diffusion programmed ROM memory compiler....

334

0.118

UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler.

UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler....

335

0.118

UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler.

UMC 0.5um Logic process standard synchronous high density single port SRAM memory compiler....

336

0.118

UMC 28nm HPC Logic process PG One Port Register File

UMC 28nm HPC Logic process PG One Port Register File...

337

0.118

UMC 28nm HPC Logic process PG One Port Register File with LVT

UMC 28nm HPC Logic process PG One Port Register File with LVT...

338

0.118

UMC 28nm HPC Logic Process PG Single Port SRAM memory compiler

UMC 28nm HPC Logic Process PG Single Port SRAM memory compiler...

339

0.118

UMC 28nm HPC Logic Process PG Single Port SRAM with LVT memory compiler

UMC 28nm HPC Logic Process PG Single Port SRAM with LVT memory compiler...

340

0.118

UMC 28nm HPC Logic Process PG Single-Port SRAM with HVT memory compiler

UMC 28nm HPC Logic Process PG Single-Port SRAM with HVT memory compiler...

341

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UMC 28nm HPC Logic process PG-One Port Register File with HVT

UMC 28nm HPC Logic process PG-One Port Register File with HVT...

342

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UMC 28nm HPC Logic Process Ultra High Density 1-Port Register File Memory Compiler

UMC 28nm HPC Logic Process Ultra High Density 1-Port Register File Memory Compiler...

343

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UMC 28nm HPC Logic Process Ultra High Density Single-Port SRAM Memory Compiler

UMC 28nm HPC Logic Process Ultra High Density Single-Port SRAM Memory Compiler...

344

0.118

UMC 28nm HPC Logic Process Via ROM Low Power Compiler with HVT peripheral

UMC 28nm HPC Logic Process Via ROM Low Power Compiler with HVT peripheral...

345

0.118

UMC 28nm HPC Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format

UMC 28nm HPC Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format...

346

0.118

UMC 28nm HPC+ Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format

UMC 28nm HPC+ Logic Process, LVDS RX Receives serial LVDS signal and de-serialize them into parallel format...

347

0.118

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track eco_m1 cell library (C35)

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track eco_m1 cell library (C35)...

348

0.118

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track generic_core cell library (C35)

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track generic_core cell library (C35)...

349

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UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track generic_core cell library (C40)

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track generic_core cell library (C40)...

350

0.118

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35)

UMC 28nm HPC/HVT Logic and Mixed-Mode Process 12-track PowerSlash cell library (C35)...

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