51 6.0

10/100 Base-TX Fast Ethernet PHY; TSMC 55nm GP ...

52 6.0

10/100 Ethernet PHY for TSMC 22nm ULP 10 100ETHERNET-T22ULP18 is a single-port DSP-based Fast Ethernet Transceiver. It contains all the ac?tive circuitry required to convert data stream to...

53 6.0

10/100 Ethernet PHY, TSMC 28nm HPC+ -10 100ETHERNET-T28HPCP18 is a single-port DSP-based Fast Ethernet Transceiver. It contains all the ac?tive circuitry required to convert data stream ...

54 6.0

24-bit 192KSPS Audio DAC ...

55 6.0

24-bit 192KSPS Audio DAC; ...

56 6.0

16-bit 48KSPS stereo Audio ADC ...

57 6.0

16-bit 48KSPS stereo Audio ADC; ...

58 6.0

Single port 10/100 Fast Ethernet Transceiver - TSMC12nm FFC SP-10 100ETHERNET-T12FFC is a single-port DSP-based Fast Ethernet Transceiver. It contains all the active circuitry required to convert data stream t...

59 6.0

MIPI D-PHY Receiver with PPI SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...

60 6.0

MIPI Rx D-PHY ...

61 6.0

USB 2.0 PHY; SMIC 40nm LL ...

62 6.0

USB 2.0 PHY; SMIC 55nm LL ...

63 6.0

USB 3.0 Device A USB 3.0 Device IP Core that provides high performance SuperSpeed USB connectivity in a small footprint solution for quick and easy implementation of...

64 6.0

LVDS 10 bits dual port transmitter ...

65 5.0

H.264/AVC 1080 60p Baseline Profile Decoder TMC's TM21745 is a decoder IP core that is compliant with ISO/IEC 14496-10 | ITU-T Rec.H.264. Using TMC's original computer algorithm, we have real...

66 5.0

H.264/AVC 1080 60p Baseline Profile Encoder - TMC's TM21745 is an encoder IP core that is compliant with ISO/IEC 14496-10 | ITU-T Rec.H.264. - Using TMC's original computer algorithm, we have...

67 5.0

H.264/AVC 4K 60p High Profile Decoder - TMC's H.264 core (RTL- IP) is designed to be compliant with the H.264 4K Video, which is a highly efficient image compression method standardized in...

68 5.0

H.264/AVC 4K 60p High Profile Encoder - TMC's H.264 core (RTL- IP) is designed to be compliant with the H.264 4K Video, which is a highly efficient image compression method standardized in...

69 5.0

H.265/HEVC 422 10bit Decoder for 4K DMNA realizes real time Encoding of 4K (3840 x 2160) and 8K (7680 x 4320) / 60fps video stream compliant with H.265 / HEVC...

70 5.0

H.265/HEVC 422 10bit Encoder for 4K DMNA realizes real time Encoding of 4K (3840 x 2160) and 8K (7680 x 4320) / 60fps video stream compliant with H.265 / HEVC...

71 5.0

H.265/HEVC H.264/AVC 422 12bit Multi-Codec for 8K TMC’s HEVC/AVC Multi-Codec IP Core for 4K/8K are designed to be compliant with the H.264 4K (4096 x 2160) Video and H.265 8K (8192 x 4320) Vid...

72 5.0

1:2 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

73 5.0

1:2 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

74 5.0

1:3 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

75 5.0

1:3 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

76 5.0

1:3 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

77 5.0

1:4 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

78 5.0

1:4 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

79 5.0

1:6 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

80 5.0

1:6 Fixed Length Visually Lossless Compression/Decompression Suppressing the degradation of image quality by the original comp./decomp. processing, drastic reductions of Memory amount and Bandwidth could be real...

81 5.0

SAS 4 Port 12G Recorder The SAS Recorder IP Core provides an ready to use solution for high speed data recording applications. Simple interface guarantees fast time to marke...

82 5.0

SAS Initiator, 12G, 4 Ports, 48 Gbps, SATA Host The SAS Initiator Controller IP Core provides an interface to high-speed serial link replacement for the parallel SCSI attachment of mass storage devi...

83 5.0

SATA Device IP Core (1.5, 3.0, 6.0 Gbps) The Serial ATA Device Controller IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage ...

84 5.0

Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s) The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The ...

85 5.0

Serial ATA Host Controller (1.5, 3.0, 6.0 Gb/s) for Xilinx UltraScale The Serial ATA Host IP Core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The ...

86 5.0

Visually LossLess compression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS) TMC’s JPEG XS encoder / decoder IP is Visually LossLess compression / decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS). T...

87 5.0

Visually LossLess decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS) TMC’s JPEG XS encoder / decoder IP is Visually LossLess decompression hardware RTL core that complies with ISO/IEC-21122-1 (JPEG XS). The logic gate ...

88 5.0

Compact LossLess Decoder RTL Core ...

89 5.0

Compact LossLess Encoder RTL Core ...

90 5.0

Lossless / Near lossless Encoder / Decoder Hardware IP - Lossless / near lossless hardware encoder and decoder IP that features compact and high speed with TMC original algorithm. - Optimized logic gate...

91 5.0

JPEG Decoder 1-pixel/clock - Baseline JPEG encoder/decoder described in RTL compliant with ISO/IEC 10918-1 - High speed processing with low clock frequency - Suitable for ...

92 5.0

JPEG Encoder 1-pixel/clock - Baseline JPEG encoder/decoder described in RTL compliant with ISO/IEC 10918-1 - High speed processing with low clock frequency - Suitable for ...

93 5.0

Frame Rate Converter for 4K TMC’s FRUC (Frame Rate Up-Converter) for 4K RTL Core utilizes proprietary ”DMNA- MEMC” (Motion Estimation and Motion Compensation) algorithm which gen...

94 4.0

Reed Solomon Decoder IP Core A high performance, fully configurable Reed Solomon Decoder IP Core that is intended for use in a wide range of applications requiring forward error c...

95 4.0

Reed Solomon Encoder IP Core A high performance, fully configurable Reed Solomon Encoder IP Core that is intended for use in a wide range of applications requiring forward error c...

96 3.0

USB 2.0 (LS, FS & HS) On-The-Go IP Core A 'Dual-Role' USB On-The-Go IP Core that operates as both an USB peripheral or as an USB OTG host in a point-to-point communications with another USB ...

97 1.0

2.5V 12Bit pipeline analog to digital converter TheS65LLV25_ADC_13 IP is a 2.5V 12Bit pipeline analog to digital converter capable of running at up to 100MHz conversion rate with 2Vp-p input range....

98 1.0

S13_DAC_03 CMOS 10-BIT 200MSPS+CURRENT-STEERING D/A Converter The S13_DAC_03 is a 10-bit resolution, high performance, low power, current-steering CMOS digital-to-analog converter (DAC). The input update rate can...

99 1.0

12-bit 1M Differential Rail to Rail SAR ADC The analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The ADC includes a core intern...

100 1.0

12-bit 8 Input 1M/200k SAR ADC) This analog-to-digital converter uses Successive Approximation Register (SAR) architecture to achieve 12-bit resolution. The IP includes a core intern...