Design & Reuse
5809 IP
2001
3.0
High-Performance Lossless Compression/Encryption Combo Core
Lossless data compression is a class of data compression algorithms that allows the exact original data to be reconstructed from the compressed data. ...
2002
3.0
MIPI D-PHY NEC 90nm
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
2003
3.0
MIPI M-PHY Designed For GF 28nm
ACS-AIP-MPHY-28HK MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A ...
2004
3.0
NIST AES Key Wrap/Unwrap Core
AKW1 implements the NIST standard AES key wrap and unwrap. Core contains the base AES core AES1 and is available for immediate licensing. The design ...
2005
3.0
Elliptic Curve Point Multiply and Verify Core
Elliptic Curve Cryptography (ECC) is a public-key cryptographic technology that uses the mathematics of so called “elliptic curves” and it is a part o...
2006
3.0
Ultra-Compact 3GPP Cipher Core
The ZUC1 core implements ZUC stream cipher in compliance with the 3GPP Confidentiality and Integrity Algorithms 128-EEA3 & 128-EIA3 version 1.6. It pr...
2007
3.0
Ultra-Compact Advanced Encryption Standard (AES, FIPS-197) Core
The AES core implements Rijndael cipher encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit data bloc...
2008
3.0
Ultra-Compact Data Encryption Standard (DES/3DES) Core
The DES1 ASIC/FPGA core is an implementation of the DES and triple DES encryption and decryption in compliance with the NIST Data Encryption Standard....
2009
3.0
eMMC 5.1 HS400 PHY and I/O Pads in TSMC 28HPM-EW
Arasan provides a HS400 compatible PHY that customers can integrate with the HS400 I/O PADs. It is designed to optimize I/O performance with a core v...
2010
3.0
SNOW 3G Encryption Core
The SNOW3G1 core implements SNOW 3G stream cipher in compliance with the ETSI SAGE specification version 1.1. It produces the keystream that consists ...
2011
3.0
FortifyIQ High-Performance Hybrid Classical and Post-Quantum High-assurance (SCA/DPA/FIA resistant) Cryptography IP Core (ECC/RSA, ML-KEM, ML-DSA)
FortifyIQ’s High-Performance Hybrid Cryptography IP core delivers accelerated support for both classical (RSA, ECC) and post-quantum (ML-KEM, ML-DSA) ...
2012
3.0
FortifyIQ HMAC-SHA256 Secure Core: Hardware Accelerator for SHA-2 and HMAC with Low Latency SCA/FI Protection
FortifyIQ’s SHA-2/HMAC IP core delivers high-speed, hardware-accelerated SHA-2-224/256 hashing and HMAC computation, optimized for secure embedded sys...
2013
3.0
FortifyIQ Hybrid Classical and Post-Quantum High-assurance (SCA/DPA/FIA resistant) Cryptography IP Core (ECC/RSA, ML-KEM, ML-DSA)
FortifyIQ’s Hybrid Cryptography IP core combines traditional asymmetric algorithms, such as RSA and ECC, with post-quantum standards including ML-KEM ...
2014
3.0
FortifyIQ's Compact DPA and FIA Hardened Post-Quantum ML-KEM IP Core for Resource-Constrained Devices (SCA/DPA/FIA resistant)
As quantum computing threatens traditional public-key cryptography, resource-constrained devices must adopt quantum-resistant algorithms without compr...
2015
3.0
FortifyIQ's Compact Post-Quantum ML-DSA Secure Cryptographic Signature IP Core for Resource-Constrained Devices (SCA/DPA/FIA resistant)
As digital signature algorithms face obsolescence in the quantum era, embedded systems require quantum-resistant alternatives that balance performance...
2016
3.0
True Random and Pseudorandom Number Generator
The true random generator core implements true random number generation. The core passes the American NIST Special Publication 800-22 and Diehard Rand...
2017
3.0
LRW-AES Core
LRW3 implements the NIST standard AES cipher in the LRW mode for encryption and decryption. The LRW3 family of cores covers a wide range of area / thr...
2018
3.0
LRW-AES Core
Implementation of the older drafts standard IEEE P1619 required the NIST standard AES cipher in the LRW mode for encryption (AES-LRW). Note that the n...
2019
3.0
LRW-AES Core
Implementation of the new encrypted shared storage media standard IEEE P1619 with AES cipher in the LRW mode....
2020
3.0
Cryptographically Secure Pseudo Random number Generator IP Core
The PRNG1 core implements a cryptographically secure pseudo-random number generator per NIST publication SP800-90. Basic core is small (6,500 gates)...
2021
3.0
Hs-Mode I2C Controller - 3.4 Mbps, Master / Slave w/FIFO
The Digital Blocks DB-I2C-MS-Hs-Mode Controller IP Core interfaces a microprocessor via the AMBA AXI / AHB / APB Bus or Avalon / Qsys Bus to an I2C Bu...
2022
3.0
RSA Public Key Exponentiation Accelerator
Rivest-Shamir-Adelman (RSA) is a public-key cryptographic technology that uses the mathematics of so called “finite field exponentiation”. The opera...
2023
3.0
USB 3.0 Device
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2024
3.0
SSL/TLS Processor IP Core with an AXI Bus Interface
The SSL1 core implements SSL and/or TLS frameworks with a configurable variety of cipher suites. SSL1-AXI has a “lookaside” interface to the rest of...
2025
3.0
XTS-AES IEEE P1619 Core Families
XTS2 and XTS3 (formerly known as XEX2 and XEX3) implement the NIST standard AES cipher in the XEX/XTS mode for encryption and decryption. The XTS3 fa...
2026
2.0
40-450MHz Programmable Clock Generator PLL, SMIC0.13um
The AR530S13 is a low power programmable phase locked loop (PLL) featured with wide output frequency range from 50MHz to 450MHz. The PLL synchronizes ...
2027
2.0
100~450MHz DDR DLL with 80 Phase Selection, SMIC0.1.3um
The AR531S13 is a low-jitter low power dual channel delay locked loop (DLL) design support for DDR application. It is featured with a wide output freq...
2028
2.0
I3C Master / Slave Controller - MIPI Basic v1.0
The Digital Blocks DB-I3C-MS-APB Controller IP Core interfaces a microprocessor via the AMBA APB Bus to an I3C Bus, compliant to the MIPI I3C – BASIC ...
2029
2.0
16-22Bit Stereo Audio CODEC with Linein/Microphone Recording, Lineout/Headphone Playback, SMIC 0.11um
The AR34S5C is a silicon-proven, low-power, ultra compact 16-22bit stereo audio CODEC IP fabricated in SMIC110nm logic process. The CODEC IP core empl...
2030
2.0
16-22Bit Stereo Audio CODEC with Microphone / Line-in Recording, Lineout / Headphone Playback, SMIC 0.13um,
The AR34S4C is a silicon-proven, low-power, ultra compact 16-22bit stereo audio CODEC IP fabricated in SMIC130nm logic process. The CODEC IP core empl...
2031
2.0
16-Bit 90dB SNR 8~48KHz stereo ADC with FM/MIC inputs, TSMC0.18um
The AR32T3D is a mass-production proven, high performance, low cost, stereo audio A/D converter designed for portable audio recording applications. Th...
2032
2.0
16-Bit 93dB Mono Sigma-Delta Audio CODEC with FM/MIC, TSMC0.18um
The AR34T3C Mono audio CODEC is a cost-down high-end solution for multi-media portable applications. It features microphone input and dual-channel hea...
2033
2.0
16-Bit >90dB SNR Stereo Audio DAC with headphone, Mono Audio ADC with microphone, Fujitsu 90nm
The AR34F5G contains a mass-production proven, low power stereo audio DAC and a mono ADC IP for portable multimedia audio applications. The IP employs...
2034
2.0
16-Bit Sigma-Delta ADC with 10 Input Channels, XFAB 0.25um
The AR32X3A specifies a silicon proven, very low power sigma-delta ADC for high-precision measurement system. The IP employs multi-bit sigma delta arc...
2035
2.0
16-Bit Sigma-Delta Stereo Audio CODEC with Microphone and Headphone, Fujitsu 65nm
The AR34F5B specifies a very low power stereo audio CODEC IP for multimedia audio system. The IP employs multibit sigma delta architecture. It include...
2036
2.0
16Bit 91dB Audio CODEC with headphone drivers and PWM Controller, SMIC0.18um
AR34S3E is a mass-production proven sigma-delta mono CODEC designed for portable device applications. It contains PWM (pulse-width-modulated) controll...
2037
2.0
16~24Bit Stereo Audio CODEC, SMIC0.18um
The AR34S1 is a 90dB multi-bit sigma-delta audio CODEC designed for low power portable applications. It requires only single 1.8V power supply to oper...
2038
2.0
Cap-less 100mA Low Noise LDO, XFAB 250nm
The LDO is capable of outputting 1.2V voltage with maximum power of 100mA and low drop out voltage of less than 200mV. The IP is fabricated in XFAB 25...
2039
2.0
Cap-less 25mA Low Noise LDO, Fujitsu 90nm
The AR25F01 is a mass-production proven cap-less LDO IP. It is capable of outputting 1.2V voltage with maximum power of 20mA and low drop out voltage ...
2040
2.0
SD 4.0 UHS-II PHY in TSMC 40LP
SD 4.0 (UHS-II) achieves a peak interface speed of 3.12 Gbps. Arasan’s UHS-II PHY is compliant with the specification of UHS-II and is an extremely ar...
2041
2.0
Gigabit Ethernet 802.3 MAC - Media Access Controller
The Gigabit Ethernet Media Access Controller with AHB Interface IP core is compliant to the Ethernet/IEEE 802.3-2008 standard. The Gigabit Ethernet - ...
2042
2.0
Single Channel UART with Scalable Rx-FIFO
Universal asynchronous receiver and transmitter (UART) using the RS232 protocol are often used to connect peripheral devices to a central controller. ...
2043
2.0
MIPI D-PHY UMC 65LL
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
2044
2.0
MIPI D-PHY - UMC 55eHV
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
2045
2.0
MIPI D-PHY Digital Front-End for FPGA
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
2046
2.0
MIPI D-PHY Global Foundries 65LPe
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
2047
2.0
MIPI D-PHY SMIC 40nm
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
2048
2.0
MIPI D-PHY TSMC 40LP eDRAM
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
2049
2.0
MIPI D-PHY TSMC 40LP Renesas- Automotive Grade
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
2050
2.0
MIPI M-PHY - UMC 40nm
MIPI M-PHY Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY config...