Design & Reuse
5460 IP
1
20.0
xSPI Flash Memory Controller
The xSPI-MC core is a versatile serial flash memory controller, which allows a system to easily detect and access the attached flash device or directl...
2
15.0
SHA-3 Secure Hash Function Core
The SHA-3 is a high-throughput, area-efficient hardware accelerator for the SHA-3 cryptographic hashing functions, compliant to NIST’s FIPS 180-4 and ...
3
10.0
I2C & SMBus Controller
The I2C-SMBUS core implements a serial interface controller for the Inter-Integrated Circuit (I2C) bus and the System Management Bus (SMBus). The cor...
4
10.0
I2C and SPI Master/Slave Controller
The I2CSPI-CTRL is a compact and versatile serial interface controller supporting both SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Cir...
5
10.0
LIN Bus Master/Slave Controller Core
Implements a communication controller that transmits and receives complete Local Interconnect Network (LIN) frames to perform serial communication acc...
6
10.0
MIPI I3C Basic Secondary Controller
The I3C-SC core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Secondary Controller core compliant with the latest MIPI I3C Basi...
7
8.0
Smart Card Reader Controller Core
Implements an interface and controller for communicating between smart cards and host systems using a variety of standard system interfaces. The SCR ...
8
5.0
HDLC & SDLC Protocol Controller
The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols. It is ba...
9
5.0
SHA-384 and SHA-512 Secure Hash Crypto Engine
The SHA-384/512 is a high-throughput, and compact hardware implementation of the SHA-384 and the SHA-512 cryptographic hash functions provisioned by t...
10
5.0
MIPI I3C Basic Target
The I3C-T core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Target controller core suitable for any I3C bus topology & complia...
11
5.0
MIPI SPMI Controller or Target
The SPMI-CTRL core implements a highly featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus. It supports th...
12
1.0
Super-Fast 8051 Microcontroller Core with Configurable Features and Peripherals
The S8051XC3 IP core implements a high-performance, low-energy, 8-bit microcontroller that executes the MCS®51 instruction set and includes a configur...
13
0.0
32-bit Deeply Embedded Processor
The BA22-DE is a compact yet powerful 32-bit processor for deeply embedded applications. It is a Harvard-style processor able to run at relatively hig...
14
0.0
32-bit/33,66Mhz PCI Host Bridge
...
15
0.0
BA22 Cache-Enabled Embedded Processor
The BA22-CE is a 32-bit processor for deeply embedded applications that use off-chip instruction and data memories and that may need to run a real-tim...
16
0.0
Hardware RTP Stack for JPEG Stream Encapsulation
Implements a Real Time Transport Protocol (RTP) hardware stack that encapsulates JPEG streams to RTP packets compliant with RFC 2435. The JPEG2RTP ca...
17
0.0
CAST Geon Secure Execution Processor for IoT
The Geon™ Secure Execution Processor is a low-power, 32-bit processor IP core with built-in protection of sensitive code and data. It uses two o...
18
0.0
PCI Master/Target Interface Core
...
19
0.0
PCI to AMBA AHB Host Bridge
This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices. The bridge enables high...
20
0.0
Secure Boot Hardware Engine
GEON-SBoot is an area-efficient, processor-agnostic hardware engine that protects SoC designs from booting with malicious or otherwise insecure code. ...
21
0.0
Secure Execution Processor
The Geon™ Secure Execution Processor is a low-power, 32-bit processor IP core with built-in protection of sensitive code and data. It uses two or more...
22
0.0
GEON Security Platform
There is a growing awareness of threats posed by devices that were traditionally not considered security critical. With rising connectivity, versatili...
23
0.0
Key Expander Core
The KEXP IP core performs AES key expansion, and is an option for the AES, AES-P and AES-GCM cores. It processes 128-bit blocks, and is programmable f...
24
0.0
AHB Multilayer Interconnect
The AHB-MLIC is a multi-layer AMBA® AHB bus fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The multilayer fa...
25
0.0
AHB Subsystem
The AHB-SBS is an integrated, verified, AMBA® 3.0 interconnect and peripherals subsystem ready for embedded applications using processors with AHB bus...
26
0.0
PipelineZero 32-bit Embedded Processor
The BA20 is a small, ultra-low-power, and very efficient 32-bit processor. It is an excellent step up from the 8051 and other 8- and 16-bit microcontr...
27
0.0
AMBA AHB to APB Bus Bridge Core
The AHB2APB implements an AHB to APB bus bridge, allowing the connection of peripherals with an APB interface to an AHB bus. The highly-configurable...
28
0.0
Internal Synchronous SRAM Controller Core
The SRAM-CTRL implements a SRAM Controller providing a standard AHB/APB interface to translate AHB/APB bus reads and writes into reads and writes with...
29
0.0
QOI Lossless Image Decompression Core
The QOID Core is a decoder that implements a highly-efficient, low-power, lossless image decompression engine compliant with the Quite OK Image format...
30
0.0
Low-Latency 10/100/1000 Ethernet MAC
The LLEMAC-1G implements an Ethernet Media Access Controller compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications. Feat...
31
0.0
APB Subsystem
The APB-SBS subsystem integrates typical microcontroller peripherals connected on the an AMBA® APB bus with a bridge to AHB or AXI bus. The subsystem ...
32
0.0
MPEG Transport Stream Multiplexing & Encapsulation Engine
The MTS-E core multiplexes and encapsulates audio, video and metadata streams in a single MPEG Transport Stream (TS), and optionally encapsulates the ...
33
0.0
ASCON Authenticated Encryption & Hashing Engine
The ASCON-F IP core is a compact, high-throughput hardware engine implementing the lightweight authenticated encryption with associated data (AEAD) an...
34
0.0
Multi-Function PCI Master/Target Interface Core
The PCI-M32MF implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up...
35
0.0
Super-Fast, Configurable 16-bit 80251 Microcontroller Core
The S80251XC3 core implements a high-performance 16-bit microcontroller that executes the MCS®251 & MCS®51 instruction sets and includes a configurabl...
36
0.0
AXI Multilayer Interconnect
The AXI-MLIC is an AMBA® AXI bus interconnect fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The AXI fabric ...
37
0.0
AXI Subsystem
The AXI-SBS is an integrated, verified, AMBA® compliant hardware/software system ready for embedded applications using processors with AXI4 interfaces...
38
0.0
AXI to APB Bridge
The AXI2APB implements a bridge between AXI and APB buses, allowing the connection of peripherals with an APB interface to an AXI bus. The highly con...
39
125.0
CAN CC, CAN FD ( CAN-FD ), CAN XL ( CAN-XL ) and TTCAN Autosar Bus Controller
The CAN-CTRL implements a highly featured and reliable CAN bus controller that performs serial communication according to the Controller Area Network ...
40
100.0
32-bit Embedded RISC-V Functional Safety Processor
The EMSA5-FS is a processor core designed for functional safety. The fault-tolerant processor uses dual or triple instances of the EMSA5, an efficient...
41
70.0
Ultra-Fast Baseline and Extended JPEG Encoder Core
This JPEG compression IP core supports the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implement...
42
50.0
Ultra-Fast Baseline and Extended JPEG Decoder Core
This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements ...
43
45.0
AES - GCM Authenticated Encryption / Decryption Security Core
The AES-GCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bi...
44
40.0
Baseline and Extended JPEG Decoder Core
The JPEG-DX-S Decoder decompresses JPEG images and the video payload for Mo-tion-JPEG container formats. It accepts compressed streams of images with ...
45
40.0
Baseline and Extended JPEG Decoder Core
The JPEG-DX-S IP core is an area-efficient, high-performance JPEG decoder conforming to the Baseline Sequential DCT and the Extended Sequential DCT mo...
46
40.0
Baseline and Extended JPEG Encoder Core
This JPEG compression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an...
47
40.0
Baseline JPEG Encoder Core
This JPEG compression IP core supports the Baseline Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-perfor...
48
40.0
Ultra-Fast AVC / H.264 Compression Baseline Profile Encoder Core
The H264-E-BPF IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. It Implements an u...
49
40.0
JPEG Lossless & Near-Lossless Compression JPEG-LS Encoder
The JPEG-LS-E core implements a highly-efficient, low-power, lossless and near-lossless image compression engine that is compliant to the JPEG-LS, ISO...
50
35.0
TSN Ethernet Endpoint Controller
The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking ...