1 100.0

32-bit Embedded RISC-V Functional Safety Processor The EMSA5-FS is a processor core designed for functional safety. The fault-tolerant processor uses dual or triple instances of the EMSA5, an efficient...

2 70.0

CAN CC, CAN FD, and CAN XL Bus Controller The CAN-CTRL implements a highly featured and reliable CAN bus controller that performs serial communication according to the Controller Area Network ...

3 50.0

Ultra-Fast Baseline and Extended JPEG Encoder Core This JPEG compression IP core supports the Baseline Sequential DCT and the Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implement...

4 45.0

AES-GCM Authenticated Encrypt/Decrypt Core The AES-GCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bi...

5 40.0

Ultra-Fast AVC/H.264 Baseline Profile Encoder Core The H264-E-BPF IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. It Implements an u...

6 25.0

1G/10G TCP/IP Hardware Stack The TCPIP-1G/10G core implements a complete TCP/IP Hardware Protocol Stack. More capable than many offloading engines, it allows systems to connect to...

7 25.0

Ultra-Fast Baseline and Extended JPEG Decoder Core This JPEG decompression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements ...

8 25.0

TSN Ethernet Endpoint Controller The TSN-EP implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking ...

9 25.0

TSN Ethernet Switch The TSN-SW implements a highly flexible, low-latency TSN Ethernet switch. It supports Ethernet bridging according to the IEEE 802.1Q-2018 standard and...

10 20.0

TSN Ethernet Switched Endpoint Controller The TSN-SE implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking ...

11 20.0

xSPI Flash Memory Controller The xSPI-MC core is a versatile serial flash memory controller, which allows a system to easily detect and access the attached flash device or directl...

12 25.0

Low-Latency AVC/H.264 Baseline Profile Decoder Core The H264-D-BP IP core is a video decoder complying with the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. It implements a...

13 15.0

SHA-3 Secure Hash Function Core The SHA-3 is a high-throughput, area-efficient hardware accelerator for the SHA-3 cryptographic hashing functions, compliant to NIST’s FIPS 180-4 and ...

14 12.0

AES-XTS for Storage Encrypt/Decrypt Core The AES-XTS encryption IP core implements encryption/decryption for sector-based storage data. It uses the AES block cypher, in compliance with the NI...

15 10.0

100G UDP/IP Hardware Protocol Stack Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...

16 10.0

40G/50G UDP/IP Hardware Protocol Stack Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...

17 10.0

I2C & SMBus Controller The I2C-SMBUS core implements a serial interface controller for the Inter-Integrated Circuit (I2C) bus and the System Management Bus (SMBus). The cor...

18 10.0

I2C and SPI Master/Slave Controller The I2CSPI-CTRL is a compact and versatile serial interface controller supporting both SPI (Serial Peripheral Interface) and I2C (Inter-Integrated Cir...

19 10.0

I2S/TDM Multichannel Audio Transceiver The I2S-TDM IP core is a highly configurable, full-duplex, multichannel serial audio transceiver. The transceiver can act as a controller (master) or ...

20 10.0

MACsec Protocol Engine for 10/100/1000 Ethernet The MAC-SEC-1G IP core implements a compact and configurable custom-hardware protocol engine for the IEEE 802.1AE (MACsec) standard. It supports all c...

21 10.0

LIN Bus Master/Slave Controller Core Implements a communication controller that transmits and receives complete Local Interconnect Network (LIN) frames to perform serial communication acc...

22 10.0

MIPI I3C Basic Secondary Controller The I3C-SC core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Secondary Controller core compliant with the latest MIPI I3C Basi...

23 8.0

Smart Card Reader Controller Core Implements an interface and controller for communicating between smart cards and host systems using a variety of standard system interfaces. The SCR ...

24 5.0

256-bit SHA Cryptoprocessor Core The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for m...

25 5.0

HDLC & SDLC Protocol Controller The HSDLC IP core implements a controller for the High-Level Data Link Control (HDLC) and the Synchronous Data Link Control (SDLC) protocols. It is ba...

26 5.0

SHA-384 and SHA-512 Secure Hash Crypto Engine The SHA-384/512 is a high-throughput, and compact hardware implementation of the SHA-384 and the SHA-512 cryptographic hash functions provisioned by t...

27 5.0

MIPI I3C Basic Target The I3C-T core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Target controller core suitable for any I3C bus topology & complia...

28 5.0

MIPI SPMI Controller or Target The SPMI-CTRL core implements a highly featured, easy-to-use controller for the MIPI System Power Management Interface (MIPI-SPMI) bus. It supports th...

29 5.0

Lossless & Near-Lossless JPEG-LS Decoder The JPEG-LS-D core implements a highly efficient and low-power, lossless and near-lossless image decompression engine that is compliant to the JPEG-LS...

30 5.0

Lossless & Near-Lossless JPEG-LS Encoder The JPEG-LS-E core implements a highly-efficient, low-power, lossless and near-lossless image compression engine that is compliant to the JPEG-LS, ISO...

31 5.0

Audio Sample Rate Converter The ASRC core is a compact and high-performance audio sample rate converter. It accurately converts digital audio signals between different sample rat...

32 4.0

AHB Cache Controller Core The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave AHB processor interface and a 32-bit master AHB interface to the...

33 1.0

10G/25G UDP/IP Hardware Protocol Stack Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...

34 1.0

Watchdog Timer with APB Interface The WDT-APB core implements 32-bit count down counter with a programmable timeout interval and logic to generate an interrupt and a reset signal on it...

35 1.0

UDP/IP Hardware Protocol Stack Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...

36 1.0

Legacy-Configurable 8051-Compatible Microcontroller The L8051XC1 core implements an MCS®51-compatible microcontroller that is specially designed to match the timing and peripherals of legacy 8051 MCU ba...

37 1.0

High-Performance, Configurable, 8-bit Microcontroller Core This 8051 IP core implements a range of fast, 8-bit, 8051-compatible microcontrollers that execute the MCS®51 instruction set. The R8051XC2 IP core r...

38 1.0

Ultra-Small 8051-Compatible Microcontroller The T8051XC3 core implements one of the smallest-available 8-bit MCS®51-compatible microcontrollers. The core integrates an 8051 CPU with a serial com...

39 1.0

Super-Fast 8051 Microcontroller Core with Configurable Features and Peripherals The S8051XC3 IP core implements a high-performance, low-energy, 8-bit microcontroller that executes the MCS®51 instruction set and includes a configur...

40 0.0

32-bit Basic Application Processor The BA22-AP is a 32-bit processor for demanding embedded applications that use off-chip instruction and data memories and that may need to run a real-...

41 0.0

32-bit Deeply Embedded Processor The BA22-DE is a compact yet powerful 32-bit processor for deeply embedded applications. It is a Harvard-style processor able to run at relatively hig...

42 0.0

32-bit, 33 MHz Multifunction Target Interface The PCI-T32MF implements a target-only PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up t...

43 0.0

32-bit, 33 MHz PCI Target Interface Core The main PCI-T32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the u...

44 0.0

32-bit/33,66Mhz PCI Host Bridge ...

45 0.0

I2C Bus Master Controller Core The I2C-MS core is a controller for the Inter-Integrated Circuit (I2C) bus. The highly configurable core can implement an I2C bus master, slave, or a ...

46 0.0

BA22 Cache-Enabled Embedded Processor The BA22-CE is a 32-bit processor for deeply embedded applications that use off-chip instruction and data memories and that may need to run a real-tim...

47 0.0

SafeSPI Controller The SafeSPI-CTRL core implements a versatile and highly reliable Serial Peripheral Interface (SPI) controller compliant with the SafeSPI specification...

48 0.0

CANsec Acceleration Engine The CAN-SEC IP core implements a hardware accelerator for the CANsec extension of the CAN-XL protocol, as defined in CiA’s 613-2 specification. The...

49 0.0

Hardware RTP Stack for JPEG Stream Encapsulation Implements a Real Time Transport Protocol (RTP) hardware stack that encapsulates JPEG streams to RTP packets compliant with RFC 2435. The JPEG2RTP ca...

50 0.0

UART with FIFOs ...