51 35.0

TSN Ethernet Switch The TSN-SW implements a highly flexible, low-latency TSN Ethernet switch. It supports Ethernet bridging according to the IEEE 802.1Q-2018 standard and...

52 25.0

1G / 10G TCP/IP Hardware Stack TCP TCPIP The TCPIP-1G/10G core implements a complete TCP/IP Hardware Protocol Stack. More capable than many offloading engines, it allows systems to connect to...

53 25.0

Low-Latency AVC / H.264 Decompression Baseline Profile Decoder Core The H264-D-BP IP core is a video decoder complying with the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. It implements a...

54 25.0

Low-Power AVC / H.264 Compression Baseline Profile Encoder Core The H264-E-BPS IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard It Implements an en...

55 25.0

JPEG Lossless & Near-Lossless Compression JPEG-LS Decoder The JPEG-LS-D core implements a highly efficient and low-power, lossless and near-lossless image decompression engine that is compliant to the JPEG-LS...

56 25.0

TSN Ethernet Switched Endpoint Controller The TSN-SE implements a configurable controller meant to ease the implementation of endpoints for networks complying to the Time Sensitive Networking ...

57 20.0

AES Encryption / Decryption Security Core The AES encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit bl...

58 12.0

AES - XTS for Storage Encryption / Decryption Security Core The AES-XTS encryption IP core implements encryption/decryption for sector-based storage data. It uses the AES block cypher, in compliance with the NI...

59 10.0

H.264 Compression High 10 Intra Profile Encoder The H264-E-HIS IP core is a video encoder compliant to the High 10 Intra profile of the ISO/IEC 14496-10/ITU-T H.264 standard. The encoder core has a ...

60 10.0

H.264 Compression Video Over IP - HD Encoder Subsystem This Video Over IP Subsystem integrates H.264 compression Transport Stream and RTP/UDP/IP encapsulation to enable the rapid development of complete vi...

61 10.0

H.264 Decompression Video Over IP – HD Decoder Subsystem This Video Over IP Subsystem integrates H.264 Decompression, Transport Stream and RTP/UDP/IP de-capsulation to enable the rapid development of complet...

62 10.0

100G UDP/IP Hardware Protocol Stack UDP UDPIP Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...

63 10.0

10G / 25G UDP/IP Hardware Protocol Stack UDP UDPIP Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...

64 10.0

40G / 50G UDP/IP Hardware Protocol Stack UDP UDPIP Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...

65 10.0

I2C Bus Master Controller Core The I2C-MS core is a controller for the Inter-Integrated Circuit (I2C) bus. The highly configurable core can implement an I2C bus master, slave, or a ...

66 10.0

I2S / TDM Multichannel Audio Transceiver The I2S-TDM IP core is a highly configurable, full-duplex, multichannel serial audio transceiver. The transceiver can act as a controller (master) or ...

67 10.0

MAC MACsec Protocol Engine for 10/100/1000 Ethernet The MAC-SEC-1G IP core implements a compact and configurable custom-hardware protocol engine for the IEEE 802.1AE (MACsec) standard. It supports all c...

68 10.0

UDP/IP Hardware Protocol Stack UDP UDPIP Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...

69 10.0

Direct Memory Access DMA Controller IP Core The DMA_CTRL core implements a low-power, single-channel Direct Memory Access (DMA) controller that is used to transfer data across a bus to and from ...

70 10.0

Motion JPEG Over IP : HD Video Compression Encoder Subsystem This Video Over IP Subsystem employs JPEG compression and RTP/UDP/IP encapsulation to enable the rapid development of complete motion JPEG video strea...

71 10.0

Programmable Mode AES Encryption / Decryption Security Core The AES-P encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit ...

72 10.0

Multi-Channel Streaming DMA Controller The MC-SDMA IP core implements a highly configurable, bandwidth-efficient, and easy-to-use Direct Memory Access (DMA) controller that transfers data b...

73 10.0

AVC / H.264 Compression Video Encoder with Compressed Frame Store The H264-E-CFS IP core is a video encoder supporting the Constrained Baseline Profile of the ISO/IEC 14496-10/ITU-T H.264 standard. It Implements an e...

74 10.0

AXI4 to/from AXI4-Stream Scatter-Gather DMA The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, which interfaces the ho...

75 10.0

AXI4 to/from Stream DMA The AXI4-DMA IP core implements a Direct Memory Access (DMA) engine that efficiently moves data between AXI4-Stream peripherals and a memory-mapped AX...

76 5.0

256-bit SHA Crypto Processor Core The SHA-256 encryption IP core is a fully compliant implementation of the Message Digest Algorithm SHA-256. It computes a 256-bit message digest for m...

77 5.0

AHB Cache Controller Core The CACHE-CTRL IP core is a flexible cache memory controller providing a 32-bit slave AHB processor interface and a 32-bit master AHB interface to the...

78 5.0

ASRC Audio Sample Rate Converter The ASRC core is a compact and high-performance audio sample rate converter. It accurately converts digital audio signals between different sample rat...

79 1.0

WDT Watchdog Timer with APB Interface The WDT-APB core implements 32-bit count down counter with a programmable timeout interval and logic to generate an interrupt and a reset signal on it...

80 1.0

Legacy-Configurable 8051 Compatible Microcontroller The L8051XC1 core implements an MCS®51-compatible microcontroller that is specially designed to match the timing and peripherals of legacy 8051 MCU ba...

81 1.0

High-Performance, Configurable, 8-bit 8051 Microcontroller Core This 8051 IP core implements a range of fast, 8-bit, 8051-compatible microcontrollers that execute the MCS®51 instruction set. The R8051XC2 IP core...

82 1.0

Ultra-Small 8051 Compatible Microcontroller The T8051XC3 core implements one of the smallest-available 8-bit MCS®51-compatible microcontrollers. The core integrates an 8051 CPU with a serial com...

83 0.0

32-bit Deeply Embedded Processor Implements a 32-bit low-power RISC processor that delivers better performance than most processors of its size. Designed for deeply-embedded systems ...

84 0.0

32-bit, 33 MHz PCI Target Interface Core The main PCI-T32 Interface core purpose is to isolate the user from having to solve complex problems of the PCI interface implementation and let the u...

85 0.0

SafeSPI SPI Controller The SafeSPI-CTRL core implements a versatile and highly reliable Serial Peripheral Interface (SPI) controller compliant with the SafeSPI specification...

86 0.0

CAN CANsec Acceleration Engine The CAN-SEC IP core implements a hardware accelerator for the CANsec extension of the CAN-XL protocol, as defined in CiA’s 613-2 specification. The...

87 0.0

Hardware RTP Stack for H.264 Stream Decapsulation Implements a Real Time Transport Protocol (RTP) hardware stack that extracts H.264/NAL streams encapsulated in RTP packets. The RTP2Η264 core is comp...

88 0.0

Hardware RTP Stack for H.264 Stream Encapsulation Implements a Real Time Transport Protocol (RTP) hardware stack that encapsulates H.264/NAL streams to RTP packets that are compliant with RFC 3894 and...

89 0.0

UART 16550 with FIFOs ...

90 0.0

UART 16750 with FIFOs, IrDA, and Synchronous CPU Interface Core The H16750S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16750 device. It performs serial-to-parallel c...

91 0.0

Master/Slave Octal SPI Controller Implements a controller for a single-, dual-, quad-, or octal-lane Serial Peripheral Interface (SPI) bus, which can operate either as a master or as a...

92 0.0

AC'97 Audio Controller The AC97-CTRL Audio Controller is a configurable IP block designed to simplify the integration of the AC'97 audio interface into ASIC and FPGA designs...

93 0.0

PCI 32-bit, 33 MHz Multifunction Target Interface The PCI-T32MF implements a target-only PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up t...

94 0.0

PCI AMBA AHB Device/Host Bridge This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices. The bridge supports H...

95 0.0

MD5 Encryption Core The MD5 encryption IP core is a fully compliant hardware implementation of the Message Digest Algorithm MD5, suitable for a variety of applications. ...

96 0.0

UDP/IP 400G Hardware Protocol Stack UDP UDPIP Implements a UDP/IP hardware protocol stack that enables high-speed communication over a LAN or a point-to-point connection. Designed for standalone o...

97 0.0

SENT / SAE J2716 Controller The CSENT core implements a controller for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and also the i...

98 0.0

AES - CCM Authenticated Encryption / Decryption Security Core The AES-CCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bi...

99 0.0

AHB / AXI4 - Lite to AXI4-Stream Bridge The MM2ST IP core bridges the streaming interfaces of a peripheral or accelerator to a memory-mapped AMBA® AHB or AXI4-Lite bus. Designed for ease ...

100 0.0

Timer / Counter with APB Interface The Timer-APB core is a 32-bit counter/timer with an APB interface that can be used to schedule periodic tasks, and can act as a high precision time r...