51 0.0

UART with FIFOs, IrDA, and Synchronous CPU Interface Core The H16750S is a standard UART providing 100% software compatibility with the popular Texas Instruments 16750 device. It performs serial-to-parallel c...

52 0.0

Baseline and Extended JPEG Decoder Core The JPEG-DX-S Decoder decompresses JPEG images and the video payload for Mo-tion-JPEG container formats. It accepts compressed streams of images with ...

53 0.0

Baseline and Extended JPEG Decoder Core The JPEG-DX-S IP core is an area-efficient, high-performance JPEG decoder conforming to the Baseline Sequential DCT and the Extended Sequential DCT mo...

54 0.0

Baseline and Extended JPEG Encoder Core This JPEG compression IP core supports the Baseline Sequential DCT and Extended Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an...

55 0.0

Baseline JPEG Encoder Core This JPEG compression IP core supports the Baseline Sequential DCT modes of the ISO/IEC 10918-1 standard. It implements an area-efficient, high-perfor...

56 0.0

CAST Geon Secure Execution Processor for IoT The Geon™ Secure Execution Processor is a low-power, 32-bit processor IP core with built-in protection of sensitive code and data. It uses two o...

57 0.0

PCI Master/Target Interface Core ...

58 0.0

PCI to AMBA AHB Host Bridge This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices. The bridge enables high...

59 0.0

Real-Time Clock with APB Interface The RTC-APB core implements a real-time clock (RTC) and calendar facility together with an alarm function. To keep track of time of day the core use...

60 0.0

Secure Boot Hardware Engine GEON-SBoot is an area-efficient, processor-agnostic hardware engine that protects SoC designs from booting with malicious or otherwise insecure code. ...

61 0.0

Secure Execution Processor The Geon™ Secure Execution Processor is a low-power, 32-bit processor IP core with built-in protection of sensitive code and data. It uses two or more...

62 0.0

General-Purpose I/O Controller Core The GPIO core is used to create functions in a system that are not implemented with dedicated controllers, and require simple input and/or output soft...

63 0.0

SENT/SAE J2716 Controller The CSENT core implements a controller for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and also the i...

64 0.0

GEON Security Platform There is a growing awareness of threats posed by devices that were traditionally not considered security critical. With rising connectivity, versatili...

65 0.0

AES Encrypt/Decrypt Core The AES encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit bl...

66 0.0

AES-CCM Authenticated Encrypt/Decrypt Core The AES-CCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bi...

67 0.0

Key Expander Core The KEXP IP core performs AES key expansion, and is an option for the AES, AES-P and AES-GCM cores. It processes 128-bit blocks, and is programmable f...

68 0.0

AHB Multilayer Interconnect The AHB-MLIC is a multi-layer AMBA® AHB bus fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The multilayer fa...

69 0.0

AHB Subsystem The AHB-SBS is an integrated, verified, AMBA® 3.0 interconnect and peripherals subsystem ready for embedded applications using processors with AHB bus...

70 0.0

Gigabit Ethernet Media Access Controller Implements an Ethernet Media Access Controller compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications. The controller pro...

71 0.0

Timer/Counter with APB Interface The Timer-APB core is a 32-bit counter/timer with an APB interface that can be used to schedule periodic tasks, and can act as a high precision time r...

72 0.0

PipelineZero 32-bit Embedded Processor The BA20 is a small, ultra-low-power, and very efficient 32-bit processor. It is an excellent step up from the 8051 and other 8- and 16-bit microcontr...

73 0.0

Direct Memory Access Controller IP Core The DMA_CTRL core implements a low-power, single-channel Direct Memory Access (DMA) controller that is used to transfer data across a bus to and from ...

74 0.0

AMBA AHB Device/Host Bridge This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices. The bridge supports Hos...

75 0.0

AMBA AHB to APB Bus Bridge Core The AHB2APB implements an AHB to APB bus bridge, allowing the connection of peripherals with an APB interface to an AHB bus. The highly-configurable...

76 0.0

SNOW-V Stream Cipher Engine The SNOW-V IP core implements the SNOW-V stream cipher mechanism, aiming to meet the security demands of modern high-speed communication systems. It c...

77 0.0

Internal Synchronous SRAM Controller Core The SRAM-CTRL implements a SRAM Controller providing a standard AHB/APB interface to translate AHB/APB bus reads and writes into reads and writes with...

78 0.0

QOI Lossless Image Decompression Core The QOID Core is a decoder that implements a highly-efficient, low-power, lossless image decompression engine compliant with the Quite OK Image format...

79 0.0

Motion JPEG Over IP : HD Video Encoder Subsystem This Video Over IP Subsystem employs JPEG compression and RTP/UDP/IP encapsulation to enable the rapid development of complete motion JPEG video strea...

80 0.0

Low-Latency 10/100/1000 Ethernet MAC The LLEMAC-1G implements an Ethernet Media Access Controller compatible with the 10/100 Mbps IEEE 802.3 and 1Gbps IEEE 802.3-2002 specifications. Feat...

81 0.0

Low-Power Deeply Embedded RISC-V Processor The BA53 is a configurable, low-power, deeply-embedded RISC-V processor IP core. It implements a single-issue, in-order, 5-stage execution pipeline, a...

82 0.0

APB Subsystem The APB-SBS subsystem integrates typical microcontroller peripherals connected on the an AMBA® APB bus with a bridge to AHB or AXI bus. The subsystem ...

83 0.0

MPEG Transport Stream Multiplexing & Encapsulation Engine The MTS-E core multiplexes and encapsulates audio, video and metadata streams in a single MPEG Transport Stream (TS), and optionally encapsulates the ...

84 0.0

Processor Core The MD5 encryption IP core is a fully compliant hardware implementation of the Message Digest Algorithm MD5, suitable for a variety of applications. ...

85 0.0

Programmable Mode AES Encrypt/Decrypt Core The AES-P encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit ...

86 0.0

ASCON Authenticated Encryption & Hashing Engine The ASCON-F IP core is a compact, high-throughput hardware engine implementing the lightweight authenticated encryption with associated data (AEAD) an...

87 0.0

Pulse Width Modulator The PWM IP core implements a compact and highly flexible Pulse Width Modulator. The core generates a repeated pattern of pulse trains of run-time conf...

88 0.0

Multi-Function PCI Master/Target Interface Core The PCI-M32MF implements a master/target PCI interface compliant with the PCI 2.3 specification. It supports a 32-bit address/data bus and operates up...

89 0.0

Super-Fast, Configurable 16-bit 80251 Microcontroller Core The S80251XC3 core implements a high-performance 16-bit microcontroller that executes the MCS®251 & MCS®51 instruction sets and includes a configurabl...

90 0.0

AXI Multilayer Interconnect The AXI-MLIC is an AMBA® AXI bus interconnect fabric connecting an arbitrary number of bus masters to an arbitrary number of slaves. The AXI fabric ...

91 0.0

AXI Subsystem The AXI-SBS is an integrated, verified, AMBA® compliant hardware/software system ready for embedded applications using processors with AXI4 interfaces...

92 0.0

AXI to APB Bridge The AXI2APB implements a bridge between AXI and APB buses, allowing the connection of peripherals with an APB interface to an AXI bus. The highly con...

93 0.0

AXI4 to/from AXI4-Stream Scatter-Gather DMA The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, which interfaces the ho...

94 0.0

AXI4 to/from Stream DMA The AXI4-DMA IP core implements a Direct Memory Access (DMA) engine that efficiently moves data between AXI4-Stream peripherals and a memory-mapped AX...

95 0.0

Synchronous UART ...

96 0.0

H.264 Video Over IP - HD Encoder Subsystem This Video Over IP Subsystem integrates H.264 compression Transport Stream and RTP/UDP/IP encapsulation to enable the rapid development of complete vi...

97 0.0

H.264 Video Over IP – HD Decoder Subsystem This Video Over IP Subsystem integrates H.264 Decompression, Transport Stream and RTP/UDP/IP de-capsulation to enable the rapid development of complet...

98 0.0

H.264, High 10 Intra Profile Encoder The H264-E-HIS IP core is a video encoder compliant to the High 10 Intra profile of the ISO/IEC 14496-10/ITU-T H.264 standard. The encoder core has a ...

99 0.0

32-bit Deeply Embedded Processor Implements a 32-bit low-power RISC processor that delivers better performance than most processors of its size. Designed for deeply-embedded systems ...

100 0.0

Hardware RTP Stack for H.264 Stream Decapsulation Implements a Real Time Transport Protocol (RTP) hardware stack that extracts H.264/NAL streams encapsulated in RTP packets. The RTP2Η264 core is comp...