201 50.0

PCIe 6.0 Controller IP The Wolley PCI Express® (PCIe®) Controller IP is a highly configurable, performance-optimized core designed for ASIC and FPGA integration. Supporting ...

202 50.0

PCIe Gen3 to SRIO Gen3 Bridge (FPGA) Mobiveil’s PCIe Gen3 to SRIO Gen3 Bridge is a high-performance FPGA-based protocol conversion IP that enables seamless communication between PCI Expre...

203 50.0

PCIe Gen5 NVMe SSD RAMDISK Reference Platform Mobiveil’s RAMDISK-Gen5is a PCIe Gen5 and 1.4 NVMe compliant Ramdisk that emulates the next generation NVMe Gen5 SSDs with high performance. With hi...

204 50.0

SD 3.0 / SDIO 3.0 / eMMC 5.0 Host Controller Arasan Chip Systems’ eMMC 5.0 / SD3.0 Host Controller IP (3MCR) is a highly integrated host controller IP solution that supports three key memory and ...

205 50.0

HDMI 2.1 Tx PHY in TSMC (16nm, 12nm, N7, N6, N6C, N4, N3E) The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...

206 50.0

HDMI 2.1/DisplayPort 2.1 TX PHY in TSMC (N3E, N3P) The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...

207 50.0

DDR5 PHY in TSMC (N5, N4P, N4C, N3P, N3E) The Synopsys DDR5/4 PHY is a complete physical layer IP interface (PHY) solution for ASIC, ASSP, and system-on-chip (SoC) applications requiring high-...

208 50.0

UFS 4.0 Host Controller compatible with M-PHY 5.0 and UniPro 2.0 The Arasan UFS Host -UniPro IP is a simple, high performance, serial interface used primarily in mobile systems between host processing and NVM mass s...

209 50.0

AHB Octal SPI Controller with PSRAM and XIP Support The Silvaco Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, usually an ind...

210 50.0

High Performance DDR5/4/3 Memory Controller Mobiveil's DDR5/4/3 Memory Controller is a highly flexible and configurable design targeted for high performance enterprise server and real-time consu...

211 50.0

MIPI C-PHY v1.0 D-PHY v1.2 TX 2 trios/2 Lanes in TSMC (12nm, N5, N3P) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

212 50.0

MIPI C-PHY v1.0 D-PHY v1.2 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3P) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

213 50.0

MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N4, N4P, N3E, N3P) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

214 50.0

MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N7, N6, N5, N4, N4C, N3E, N3P) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

215 50.0

MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N6, N6C, N5, N4P, N4C, N3) Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...

216 50.0

MIPI D-PHY Universal Tx / Rx v1.1 @1.5ghz Ultra Low Power for IoT & Wearables Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on TSMC 22nm process technology for SoC designs. Arasan’s D-PHY IP is ava...

217 50.0

MIPI DSI-2 Receiver Controller v1.0 The Arasan DSI-2 Device Controller IP is designed to provide MIPI DSI-2 1.0 compliant high speed serial connectivity for mobile display modules with T...

218 50.0

MIPI M-PHY - TSMC 40nm MIPI M-PHY Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY config...

219 50.0

MIPI M-PHY G4 Type 1 2Tx2RX in TSMC (16nm, 12nm, N7, N6, N5, N4, N3A, N3E) The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v5.0 specification, supports speeds up to 23.32 Gbps per lane. The I...

220 50.0

Ultra High-Speed Cache Memory Compiler Silvaco’s Ultra High-Speed cache memory is an adaptable, independent, non-coherent cache Intellectual Property (IP) featuring an advanced cache ar...

221 50.0

ONFI 3.2 NV-DDR2 PHY in GDSII Compliant to ONFI 3.2 electrical interface, Arasan ONFI 3.2 PHY, delivered in hard macro, is process technology proven and easy to integrate. This ON...

222 50.0

ONFI 4.0 NAND Flash Controller & PHY The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP is changing with it. New applications are emerging and innovative IP solu...

223 50.0

ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP Core is changing in accordance with it. New applications are emerging and...

224 50.0

ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP Core is changing in accordance with it. New applications are emerging and...

225 50.0

Low-power, high-speed 12-bit 4GSPS SAR (ADC) TSMC 28nm HPC+ The A12B4G is a low-power, high-speed analog to digital converter (ADC) intellectually property (IP) design block. It is a time interleaved (TI) succe...

226 50.0

Low-power, high-speed 12-bit, 8 GSPS Analog to Digital Converter (ADC) IP block TSMC 28nm HPC+ process The A12B8G is a low-power, high-speed analog to digital converter (ADC) intellectually property (IP) design block. It is a time interleaved (TI) succe...

227 50.0

LPDDR5/4x/4 combo PHY on 14nm, 12nm OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...

228 50.0

LPDDR5X/5/4X PHY in TSMC (N5, N4P, N4C, N3E, N3P, N3A) The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...

229 50.0

USB 2.0 nanoPHY in SMIC (65nm) The Synopsys USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low-power mobile and consumer applicati...

230 50.0

USB 3.1 PHY (10G/5G) inTSMC (16nm, 12nm, N7, N6, N5,N3E, N3P) The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...

231 50.0

USB-C 3.1 DP/TX PHY ebdaux in TSMC (N6C, N5, N4P, N4C, N3E) The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...

232 50.0

USB-C 3.2 DP/TX PHY in TSMC (N3E) The Synopsys USB-C 3.2/DisplayPort 1.4 IP solution consists of USB-C 3.2/DisplayPort 1.4 PHYs, USB-C 3.2/DisplayPort 1.4 controllers (Device, Host, or...

233 50.0

USB-C 3.2 SS/SSP PHY in Type-C in TSMC (N7, N6, N5, N3E) The Synopsys SuperSpeed 3.2 USB IP solution is based on the USB 3.2 specification from the USB Implementer Forum. The USB 3.2 IP offering includes con...

234 50.0

TSMC 3nm (N3E) 1.2V LVDS Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

235 50.0

TSMC 3nm (N3E) 1.2V/1.8V GPIO Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

236 50.0

TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

237 50.0

TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries, multiple metalstacks Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

238 50.0

TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

239 50.0

TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries, multiple metalstacks Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...

240 50.0

TSMC 3nm (N3E) 1.5V LVDS Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...

241 50.0

TSMC 3nm (N3E) 1.8V SD/eMMC IO Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

242 50.0

TSMC 3nm (N3E) 1.8V SD/eMMC PHY Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

243 50.0

TSMC 3nm (N3E) 1.8V SD/eMMC PHY, multiple metalstacks Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...

244 50.0

TSMC 3nm (N3E) GPIO Basekit Libraries Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...

245 50.0

Quad SPI Controller The Serial Peripheral Interface or SPI-bus is a simple 4- wire serial communications interface used by many peripheral chips that enable the controlle...

246 50.0

Hyperbus Flash Memory Controller Emerging high-performance applications demand increasingly fast read throughputs from NOR-flash memory devices. At the same time, the pin-count requir...

247 46.0

32Gbps, 31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps. Error count is accurate: no double counts or omissions reg...

248 46.0

32Gbps, 7/15 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7 or 15 order, up to 32Gbps. Error count is accurate: no double counts or omission...

249 46.0

32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7, 15 or 31 order, up to 32Gbps. Error count is accurate: no double counts or omis...

250 40.0

RapidIO Controller with V4.1 Support Mobiveil's RapidIO Controller solution (GRIO) is a highly flexible and configurable IP. The Mobiveil RapidIO Controller Solution can be used as a Host...