Design & Reuse
Catalog of SIP Cores
System on Chip design resources
3751 IP
151
10.0
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY...
152
10.0
64x8 Bits OTP (One-Time Programmable) IP, UM- 55nm ULP standard CMOS core logic Process
The AT64X8U55ULP6AA is organized as a 64-word by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in 55nm ULP standard ...
153
10.0
64x8 Bits OTP (One-Time Programmable) IP, X-FA- 0.18μm XH018 Modular Mixed Signal Process
The ATO00064X8XH180TG33NA is organized as a 64-bit by 8 one-time programmable (OTP). This is a type of non-volatile memory fabricated in X-FA- 0.18μm ...
154
10.0
256x8 Bits OTP (One-Time Programmable) IP, TSM- 22ULP 0.8V/1.8V process
The AT256X8T22ULP6AA is organized as 256 bits by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in TSM- 22nm ULP CMOS...
155
10.0
768x39 Bits OTP (One-Time Programmable) IP, TSM- 55ULP 0.9V–1.2V / 2.5V Process
The ATO0768X39TS055ULP4NA is organized as 768x39 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSM- 55nm LP 1.2V/2....
156
10.0
16Kx33 Bits OTP (One-Time Programmable) IP, TSM- 40LP 1.1V/2.5V Process
The ATO016KX33TS040LLP7ZA is organized as 16K-bits by 33 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSM- 40nm ...
157
10.0
HBM3 PHY IP at 7nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
158
10.0
GDDR6 PHY IP for 12nm
OPENEDGES, the memory system IP provider, including DDR memory controller, DDR PHY, on-chip interconnect, and NPU IP together as an integrated solutio...
159
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY...
160
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY (in production)...
161
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY...
162
10.0
Gigabit Ethernet PHY
Gigabit Ethernet PHY...
163
10.0
Gigabit Ethernet PHY (Modification Right)
Gigabit Ethernet PHY Modification Right (in production)...
164
10.0
RISC-V Vector Unit
A Vector Unit is composed of several 'vector cores', roughly equivalent to a GPU core, that perform multiple calculations in parallel. Each vector cor...
165
10.0
4Kx16 Bits OTP (One-Time Programmable) IP, UM- 110 nm 1.2V/3.3V L110AE Process
The AT4K16U110MAE0DA is organized as a 4K-bits by 16 one-time programmable memory. This is a kind of non-volatile memory fabricated in UM- L110AE proc...
166
10.0
4Kx32 Bits OTP (One-Time Programmable) IP, TSM- 40nm ULP 1.1V/2.5V Process
The AT4K32T40ULP7ZC is organized as 4K-bits by 32 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSM- 40nm ULP stand...
167
10.0
4Kx8 Bits OTP (One-Time Programmable) IP, GLOBA-FOUNDR---® 22nm FDX 0.8V/1.8V Process
The AT4K8G22FDX0AA is organized as a 4K-bits by 8 one-time programmable memory. This is a kind of non-volatile memory fabricated in GLOBA-FOUNDR---® ...
168
10.0
8Kx8 Bits OTP (One-Time Programmable) IP, VI- 0.15µm 1.8V/5V BCD GIII Process
The AT8K8V150BCD0DB is organized as an 8K-bit by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in VI- 0.15μm BCD GII...
169
10.0
OneStar Technology Engineering Services
OneStar Technology is a professional Silicon Intellectual Property (SIP) solution provider, while also offers Electronic Design Automation (EDA), Comp...
170
10.0
UniPro 1.6 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
171
10.0
UniPro 1.8 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
172
10.0
UniPro 1.8 Host/Device IP
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
173
10.0
UniPro Controller 2.0 IP (host / device)
The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...
174
10.0
USB 3.2 Gen2/Gen1 PHY IP in TSMC(3nm, 5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps. It is compl...
175
10.0
1x64 Bits OTP (One-Time Programmable) IP, Globa-Foundr--- 22nmFDX 0.8V/1.8V Process
The AT1X64G22FDX0AA is organized as a 1 by 64 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in Globa-Foundr--- 22nm FD...
176
8.0
10/100 Base-TX Fast Ethernet PHY; SMIC 40nm LL
SP-10_100_Ethernet-S40LL is a single-port DSP-based Fast Ethernet Transceiver. It contains all the active circuitry required to convert data stream to...
177
8.0
10/100 Ethernet PHY for TSMC 22nm ULP
10 100ETHERNET-T22ULP18 is a single-port DSP-based Fast Ethernet Transceiver. It contains all the ac?tive circuitry required to convert data stream to...
178
8.0
10/100 Ethernet PHY, TSMC 28nm HPC+
-10 100ETHERNET-T28HPCP18 is a single-port DSP-based Fast Ethernet Transceiver. It contains all the ac?tive circuitry required to convert data stream ...
179
8.0
Single port 10/100 Fast Ethernet Transceiver - TSMC12nm FFC
SP-10 100ETHERNET-T12FFC is a single-port DSP-based Fast Ethernet Transceiver. It contains all the active circuitry required to convert data stream t...
180
6.0
2-ch 16-bit stereo Audio ADC
...
181
6.0
2-ch 16-bit stereo Audio ADC
...
182
6.0
2-ch 24-bit 192KSPS Audio DAC
...
183
6.0
2-ch 24-bit 192KSPS Audio DAC
...
184
6.0
2-ch 24-bit 192KSPS Audio DAC; TSMC 40nm LP
...
185
6.0
10-bit dual-port 30MHz ~ 85MHz LVDS Tx;
...
186
6.0
10/100 Base-TX Fast Ethernet PHY; TSMC 55nm GP
...
187
6.0
24-bit 192KSPS Audio DAC
...
188
6.0
24-bit 192KSPS Audio DAC;
...
189
6.0
16-bit 48KSPS stereo Audio ADC
...
190
6.0
16-bit 48KSPS stereo Audio ADC;
...
191
6.0
Technology Development Services
CSEM – Pioneering Ultra-Low Power ASIC and SoC Innovation CSEM is a Swiss public-private, non-profit technology innovation center with over 40 year...
192
6.0
MIPI D-PHY Receiver with PPI
SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...
193
6.0
MIPI D-PHY Receiver with PPI
SP_MIPI_DPHY_RX_PPI _T28HPCP is a MIPI D-PHY Receiver, which complies with MIPI D-PHY specification version 1.2. This D-PHY design receives data from ...
194
6.0
MIPI Rx D-PHY
...
195
6.0
LPDDR4/DDR4/DDR3 PHY - TSMC 22nmULL
SP-LPD4/D43_PHY16BIT-T22ULL is designed for DRAM controller to connect to the LPDDR4/DDR4/3 DRAM memory device. It contains a DDR PHY Control Unit(DPC...
196
6.0
USB 2.0 PHY; SMIC 40nm LL
...
197
6.0
USB 2.0 PHY; SMIC 55nm LL
...
198
6.0
LVDS 10 bits dual port transmitter
...
199
5.0
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP (DSP)
The 32-bit D45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compr...
200
5.0
32-bit 8-stage superscalar processor that supports RISC-V specification, including GCNP and Linux
The 32-bit A45 is an 8-stage superscalar processor that supports RISC-V specification, including “G” (“IMAFD”) standard instructions, “C” 16-bit compr...