Design & Reuse
5161 IP
1301
10.0
Differential Clock Receiver to CML - TSMC CLN2P
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
1302
10.0
Differential Clock Receiver to CML - TSMC CLN3A
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
1303
10.0
Differential Clock Receiver to CML - TSMC CLN3E
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
1304
10.0
Differential Clock Receiver to CML - TSMC CLN6FF
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
1305
10.0
Differential Clock Reciever - TSMC CLN3P
Analog Bits’ Differential Clock Receiver macro addresses a large portfolio of applications. The Receiver is designed for digital logic processes and u...
1306
10.0
Differential Clock Reciever to CML - TSMC CLN3P
Analog Bits’ Differential Clock Receiver to CML macro is a receiver including on-chip termination, and addresses a large portfolio of applications req...
1307
10.0
Differential Output Buffer - TSMC CLN3P
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a...
1308
10.0
Differential Output Buffer - TSMC 6FF
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1309
10.0
Differential Output Buffer - TSMC CLN3E
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1310
10.0
Differential Output Buffer - TSMC CLN3P
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1311
10.0
Differential Output Buffer - TSMC CLN4P
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1312
10.0
Differential Output Buffer - TSMC N5
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1313
10.0
Differential Output Driver - TSMC CLN2P
Analog Bits’ Differential Output Driver macros provide a low noise, high performance differential output clock. The output driver design implements a ...
1314
10.0
Differential Receiver - TSMC 7FF
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
1315
10.0
Differential Signal Receiver - TSMC 6FF
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
1316
10.0
Differential Signal Receiver - TSMC N5
Analog Bits Differential Signal Receiver macro is a receiver including on-chip termination, and addresses a large portfolio of applications. The Recei...
1317
10.0
High Performance 1-22.5G PCIe4/SAS4 PHY - TSMC 16FFC
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protoc...
1318
10.0
High Performance 20GHz C2C PLL - TSMC CLN3A
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1319
10.0
High Performance 20GHz C2C PLL - TSMC CLN3E
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1320
10.0
High Performance 20GHz C2C PLL - TSMC CLN6FF
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1321
10.0
High Performance 20GHz PLL - TSMC CLN4P
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1322
10.0
High Performance 20GHz PLL - TSMC CLN5A
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1323
10.0
High Precision Temp Sensor - TSMC CLN2P
Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...
1324
10.0
High Precision Temp Sensor - TSMC CLN3A
Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...
1325
10.0
High Precision Temp Sensor - TSMC CLN3E
Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...
1326
10.0
High Precision Temp Sensor - TSMC CLN5A
Analog Bits' High Accuracy Thermometer is a highly integrated macro for monitoring temperature variation on-chip, allowing very high precision even in...
1327
10.0
High Speed 20GHz PLL - TSMC CLN6FF
Analog Bits’ High Speed PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous inter...
1328
10.0
High Speed PLL - TSMC N4P
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
1329
10.0
High Speed PLL - TSMC N5
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
1330
10.0
High Speed PLL - TSMC N5A
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
1331
10.0
High Speed PLL - TSMC N5A
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
1332
10.0
High Speed PLL CML to Complementary - TSMC CLN3P
Analog Bits’ High Speed 20GHz PLL creates a high speed clock with good duty cycle and jitter characteristics useful for high speed, source synchronous...
1333
10.0
Highly scalable inference NPU IP for next-gen AI applications
OPENEDGES, the total memory subsystem IP provider, introduces ENLIGHT Pro, a state-of-the-art inference neural processing unit (NPU) IP that outperfor...
1334
10.0
TileLink Target
TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and other slave devices. Ti...
1335
10.0
LIN Bus Master/Slave Controller Core
Implements a communication controller that transmits and receives complete Local Interconnect Network (LIN) frames to perform serial communication acc...
1336
10.0
MIPI C-PHY v1.2 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (16nm) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1337
10.0
MIPI C-PHY v1.2 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (16nm, N7) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1338
10.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 2 trios/2 Lanes in TSMC (16nm) for Automotive
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1339
10.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, N7, N5A, N3A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1340
10.0
MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N5A, N3A)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
1341
10.0
MIPI D-PHY TSMC 130nm
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
1342
10.0
MIPI D-PHY TSMC 28nm HPC+ @ 2.5Ghz
The Arasan’s MIPI D-PHY Analog Transceiver IP Core is fully compliant to the D-PHY specification version 1.1. It supports the MIPI® Camera Serial Inte...
1343
10.0
MIPI D-PHY Tx-Only 2 Lanes in TSMC (16nm, N7) for Automotive
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
1344
10.0
MIPI D-PHY Tx-Only 4 Lanes in TSMC (16nm, N7) for Automotive
Synopsys’ IP D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral devices for m...
1345
10.0
MIPI DSI-2 Transmit Controller v1.0
The Arasan DSI-2 Device Controller IP is designed to provide MIPI DSI-2 1.0 compliant high speed serial connectivity for mobile host processors using ...
1346
10.0
MIPI I3C Basic Secondary Controller
The I3C-SC core implements a versatile MIPI® Improved Inter Integrated Circuit (I3C) Secondary Controller core compliant with the latest MIPI I3C Basi...
1347
10.0
MIPI I3C PHY I/O
Arasan’s MIPI I3CⓇ PHY I/O IP, in compliance with MIPI I3CⓇ specifications v1.1. Arasan’s MIPI I3CⓇ PHY IP is part of Arasan’s Total IP Solution for M...
1348
10.0
MIPI M-PHY Designed For TSMC 28nm
ACS-AIP-MPHY-28HPM MIPI Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A...
1349
10.0
MIPI M-PHY G4 Designed For TSMC 28nm HPC+
ACS-AIP-MPHY-28HPC+ MIPI Specification Version 4.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. ...
1350
10.0
Wishbone Target
The Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a versatile design approach for semiconductor IP cores. Its go...