Design & Reuse
5163 IP
2851
0.0
PCIe 6.0 PHY IP for TSMC N5
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...
2852
0.0
PCIe 6.0 PHY NCS IP for TSMC (N3E, N3P)
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency across network interfac...
2853
0.0
PCIe 7.0 Controller (can be configured to support EP, RP, DM, or SW applications)
The configurable and scalable Synopsys Controller IP for PCI Express® (PCIe®) 7.0 supports all required features of the PCI Express 7.0 specification,...
2854
0.0
PCIe 7.0 Controller with AXI
The Rambus PCI Express® (PCIe®) 7.0 Controller with AXI is a configurable and scalable design for ASIC implementations. It is backward compatible to P...
2855
0.0
PCIe 7.0 Integrity and Data Encryption (IDE) Security IP Module
PCI Express is a ubiquitous interface for a wide variety of applications, from connecting accelerators and peripheral devices to data center servers t...
2856
0.0
PCIe 7.0 PHY for TSMC N5
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...
2857
0.0
PCIe 7.0 PHY in Samsung (SF4X)
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...
2858
0.0
PCIe 7.0 PHY in TSMC (N7A, N5A, N3A) for Automotive
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 7.0 meets today’s demands for higher bandwidth and power efficiency across backplane, and c...
2859
0.0
UCIe Controller for Streaming Protocols
Synopsys UCIe Controller IP is comprised of the Die-to-Die Adapter layer and Protocol layer for widely used protocols such as PCI Express and CXL. The...
2860
0.0
PCIe Controller Testbench
PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design. This includes the following features: • R...
2861
0.0
UCIe PHY IP on TSMC N3P
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
2862
0.0
UCIe PHY on Samsung SF5A
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...
2863
0.0
UCIe PHY on TSMC N3E
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netwo...
2864
0.0
PCIe Switch for USB4 Hubs, Hosts and Devices
Rambus PCIe Multi-port Switch for USB4 is a customizable, embedded Switch for PCI Express (PCIe) designed for implementations in USB4 devices. A fully...
2865
0.0
UCIe-A PHY for Advanced Package (x64) in Samsung (SF2)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
2866
0.0
UCIe-A PHY for Advanced Package (x64) in Samsung (SF4X)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
2867
0.0
UCIe-A PHY for Advanced Package (x64) in TSMC (N5)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
2868
0.0
UCIE-A PHY, 5nm/4nm
The InPsytech (IPT) UCIe-A PHY is a mass-production proven, state-of-the-art physical layer interface designed to provide exceptional performance and ...
2869
0.0
UCIE-A PHY, ADVANCED PACKAGE
The InPsytech (IPT) UCIe-A PHY is a state-of-the-art physical layer interface, offering industry-leading power efficiency and proven in mass productio...
2870
0.0
UCIe-S (Gen2) Compatible PHY for Standard Package (x16) in TSMC (N3P)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
2871
0.0
UCIe-S PHY for Standard Package (x16) for Automotive in TSMC (N5A)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
2872
0.0
UCIe-S PHY for Standard Package (x32) in TSMC (N3P)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and netw...
2873
0.0
CCIR 656 Decoder
The Digital Blocks DB1840 CCIR 656 Decoder IP Core decodes an ITU-R BT.656 digital video uncompressed NTSC 720x486 (525/60 Video System) and PAL 720x5...
2874
0.0
CCIR 656 Encoder
The Digital Blocks DB1830 CCIR 656 Encoder IP Core encodes 4:2:2 Y’CbCr component digital video with synchronization signals to conform to NTSC & PAL ...
2875
0.0
PCM to Class D Amplifier
The AR35S13B is a high-performance digital Class D Amplifier IP for mono speaker playback application. The amplifier converts 16-24 bits digital PCM (...
2876
0.0
ACS-AIP-DPHY-40GF-Auto - MIPI D-PHY in GlobalFoundries 40nm Automotive Process
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
2877
0.0
ACS-AIP-DPHY-40LP-RA - MIPI D-PHY TSMC 40LP Renesas- Automotive Grade
Arasan delivers you a MIPI D-PHY in the process node and lane configuration you need, conforming to your specific design constraints, with a complete ...
2878
0.0
3D GPU compatible with OpenGL ES (3D Graphics API) and OpenCL (Computing API)
DMP M3000 3D GPU IP Core adopts 3rd generation 3D graphics architecture Musashi and make remarkable progress in PPA (Power, Performance, Area) perform...
2879
0.0
3D GPU supporting OpenGL ES2.0 capability
The DMP ant300 is the world’s smallest class 3D graphics IP core supporting OpenGL ES2.0 capability. It is the premiere solution for popular ASIC/ASSP...
2880
0.0
2D Graphics IP Core
DMP K3000 2D GPU IP Core offers the most powerful rendering performance in the industry, with a minimum area solution. You will witness blazing font a...
2881
0.0
2D Graphics Rendering Engine
Digital Blocks 2D Graphics Hardware Accelerator Verilog IP Cores consists of the DB9200AXI4, DB9200AXI, DB9200AHB, and DB9200AVLN. The DB9200 2D Graph...
2882
0.0
SD UHS-II PHY IP
SLI PSDUHS2A_PHY is PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed interface f...
2883
0.0
SD UHS-III PHY (UHS-II Gen2) IP
SLIPSDUHS3A_PHY is PHY IP solution for UHS-II interface that SD Association is working on the standardization as the new ultra high speed interface fo...
2884
0.0
MD5 Hashing Core
The es1005 hash fully implements the MD5 (Message Digest Algorithm RFC 1321). The core can be used for data authentication in digital broadband, wire...
2885
0.0
VDC-M (VESA Display Compression-M) Decoder
The Rambus VESA VDC-M 1.2 Decoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliv...
2886
0.0
VDC-M (VESA Display Compression-M) Encoder
The Rambus VESA VDC-M 1.2 Encoder IP Core (formerly from Hardent) implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 encoder to deliv...
2887
0.0
HDCP 2.0 Encryption Suite
HDCP Suite consists of hardware and software components implementing the HDCP 2.0 protocol. The hardware components are fully synchronous and availabl...
2888
0.0
HDCP Encryption-Decryption Engine
The Trilinear Technologies High-bandwidth Digital Content Protection (HDCP) Encryption-Decryption Engine IP core allows system designers to accelerate...
2889
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HDCP Engine
The EIP-116 High-bandwidth Digital Content Protection Control Path module provides the required technology for implementing all the secure access, cry...
2890
0.0
GDDR6 Memory PHY for TSMC N5P
Designed for high performance and low latency in AI/ML, graphics and networking The latest, the Denali PHY IP for GDDR6, is comprised of architectura...
2891
0.0
GDDR6 Memory PHY for TSMC N7
Designed for high performance and low latency in AI/ML, graphics and networking The latest, the Denali PHY IP for GDDR6, is comprised of architectura...
2892
0.0
GDDR6 PHY for TSMC N6
High-performance IP for graphics, AI/ML, and automotive products The latest, the Denali PHY IP for GDDR6, is comprised of architectural improvements ...
2893
0.0
GDDR7 Memory PHY for TSMC N3P
High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving hig...
2894
0.0
GDDR7 Memory PHY for TSMC N4P
High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving high-...
2895
0.0
GDDR7 Memory PHY for TSMC N5P
High performance for graphics, AI, and automotive products The Cadence IP solution for GDDR7 consists of high-performance hardened PHY, serving high-...
2896
0.0
SDIO HOST VMM based Verification IP
The Secure Digital Input Output (SDIO) interface is a card interface defined to connect a SD Host Controller with four different types of cards, namel...
2897
0.0
3DIO PHY IP for TSMC N5
Synopsys 3DIO is a specialized IO for multi-die integration. It includes multiple IP offerings for system-on-chip (SoC) designers to implement tunable...
2898
0.0
HDMI 2.1 Forward Error Correction (FEC) Receiver
The HDMI Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol de-interleaving/de-mapping as specified by the HDMI 2....
2899
0.0
HDMI 2.1 Forward Error Correction (FEC) Transmitter
The HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specified by the HDMI 2.1 ...
2900
0.0
HDMI 2.1/DisplayPort 2.1 TX PHY in Samsung (SF5A)
The Synopsys HDMI 2.1 TX Controller and PHY IP solutions,compliant with the High-Definition Multimedia Interface (HDMI) 2.1 specification, provide the...