Design & Reuse
5163 IP
2951
0.0
memBrain™ Tile
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2952
0.0
General Purpose Input / Output Controller (GPIO)
This general purpose input/ output controller provides some unique features that eases system integration and use. Each GPIO port can be configured fo...
2953
0.0
General Purpose Integer Hybrid PLL, CLN28HPC/HPC+, 80MHz - 8000MHz
Kamaten Integer-N Hybrid (Analog with Digital Aid) PLL generates clock signals within broad frequency range. Division coefficients of the built-in inp...
2954
0.0
General-Purpose I/O Controller Core
The GPIO core is used to create functions in a system that are not implemented with dedicated controllers, and require simple input and/or output soft...
2955
0.0
Tensilica ConnX 220/230
Ultra-high performance supports rich data types and accelerations for the computation needs in the compute chain of radar, lidar The Cadence Tensilic...
2956
0.0
Tensilica ConnX 220/230
Ultra-high performance supports rich data types and accelerations for the computation needs in the compute chain of radar, lidar The Cadence Tensilic...
2957
0.0
Tensilica HiFi 5s DSP
Performance leader melding AI/ML, audio/voice, and lightweight vision DSP performance with auto-vectorization for fast time to m Blending a neural ne...
2958
0.0
Tensilica MathX 110/130 DSPs
High-performance DSPs designed for floating-point-centric processing with ultra-low energy and small area Cadence® Tensilica® FloatingPoint KP1/KP6 D...
2959
0.0
Tensilica MathX 230/240 DSPs
Super-high-performance DSPs specifically optimized for floating-point workload with exceptional PPA Cadence® Tensilica® FloatingPoint KQ7 and KQ8 DSP...
2960
0.0
Tensilica NeuroEdge AI Co-Processor
The NeuroEdge AI Co-Processor (AICP) is Cadence s latest addition to the Tensilica family. This innovative processor is specifically designed to work ...
2961
0.0
Tensilica Vision 110 DSP
Vision DSP, built using 128-bit SIMD and offering up to 0.45 TOPs of performance for embedded vision and AI The Cadence® Tensilica® Vision P1 DSP is ...
2962
0.0
Tensilica Vision 130 DSP
Vision DSP, built using 512-bit SIMD and offering up to 1.08 TOPs of performance for embedded vision and AI The Cadence® Tensilica® Vision P6 DSP, in...
2963
0.0
Tensilica Vision 230 DSP
Built on our latest Xtensa NX architecture and offers up to 2.18TOPS of performance...
2964
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Tensilica Vision 240 DSP
Built using 1024-bit SIMD and offering up to 3.84TOPS of performance...
2965
0.0
Tensilica Vision 331 DSP
512-bit SIMD, a single DSP for vision, radar, lidar, and AI. Offers up to 2.11 TOPS of performance The Cadence® Tensilica® Vision Q7 DSP delivers up ...
2966
0.0
Tensilica Vision 341 DSP
Built using 1024-bit SIMD, single DSP for vision, radar, lidar, and AI and offering up to 4.22 TOPS of performance The Cadence® Tensilica® Vision Q8 ...
2967
0.0
SENT/SAE J2716 Controller
The CSENT core implements a controller for the Single Edge Nibble Transmission (SENT) protocol. It complies with the SAE J2716 standard and also the i...
2968
0.0
Neo NPU - Scalable and Power-Efficient Neural Processing Units
Highly scalable performance for classic and generative on-device and edge AI solutions The Cadence Neo NPUs offer energy-efficient hardware-based AI ...
2969
0.0
GEON Security Platform
There is a growing awareness of threats posed by devices that were traditionally not considered security critical. With rising connectivity, versatili...
2970
0.0
NeoPUF - an ideal security solution for IoT
NeoPUF is a hardware security technology based on the physical unclonable variations occurring in silicon manufacturing process. The underlying benefi...
2971
0.0
Reorder Core
The Reorder Core from Rambus reorders requests based on first on priority and second on throughput optimization. Throughput optimization includes m...
2972
0.0
Performance modeling using stochastic components
Evaluate The System Architecture And Generate Latency/Throughput Graphs. In stochastic modeling, different channels need to be modeled for each input-...
2973
0.0
Performance P870/P870A
The highest performance RISC-V core is ideal for consumer applications or used in conjunction with a vector processor in the datacenter. The P870 sets...
2974
0.0
Verification IP for DDR3 (UDIMM, RDIMM, LDIMM)
Synopsys® VC VerificationIP for the JEDEC DDR3 memory protocol specification provides a comprehensive set of protocol, methodology, verification and p...
2975
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Verification IP for DDR3 (UDIMM, RDIMM, LDIMM)
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2976
0.0
Certified ASIL B & ISO 21434 Cybersecurity Compliant PCIe 5.0 Integrity and Data Encryption Security Module
PCI Express is a ubiquitous interface for a wide variety of applications, from connecting accelerators and peripheral devices to data center servers t...
2977
0.0
AES + SHA DMA Crypto Accelerator
The EIP-120 is a low-power low-gatecount crypto core with DMA capability and local key storage. Compared to a software only solution, the core provide...
2978
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AES Core
The es4001 AES core implements the Advanced Encryption Standard (Rijndael Algorithm FIPS 197) encoder and decoder. The core encrypts and decrypts in b...
2979
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DES Core - Low-gate count Data Encryption Standard
ES1040 core implements Data Encryption Standard (DES) cipher algorithms in hardware. DES is a block cipher, works on blocks of 64 bits of data using 6...
2980
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AES Encrypt/Decrypt Core
The AES encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bit bl...
2981
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AES Key Wrap Crypto Accelerator
The EIP-37 is the IP for accelerating the AES Key Wrap cipher algorithm (NIST-Key-Wrap & RFC3394). Designed for fast integration, low gate count and f...
2982
0.0
AES-CCM Authenticated Encrypt/Decrypt Core
The AES-CCM encryption IP core implements Rijndael encoding and decoding in compliance with the NIST Advanced Encryption Standard. It processes 128-bi...
2983
0.0
AES-ECB 1 Billion Trace DPA & Fault Injection Resistant Crypto Accelerator
Rambus DPA & Fault Injection Resistant AES-ECB Cryptographic Cores prevent against the leakage of secret cryptographic key material through attacks wh...
2984
0.0
AES-ECB 1 Billion Trace DPA Resistant Crypto Accelerator
Rambus Crypto Accelerator AES-AE–Fast Hardware Cores offload compute intensive cryptographic algorithms in SoC’s CPU at 100x performance (when run at ...
2985
0.0
AES-ECB Accelerator
The EIP-32 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publ...
2986
0.0
AES-ECB-CBC-CFB-CTR 1 Billion Trace DPA Resistant Crypto Accelerator
Rambus DPA Resistant AES-FBC Cryptographic Accelerator Cores offload compute intensive cryptographic algorithms in SoC’s CPU at 100x performance (when...
2987
0.0
AES-ECB-CBC-CFB-CTR-GCM 1 Billion Trace DPA & Fault Injection Resistant Crypto Accelerator
Rambus DPA & Fault Injection Resistant AES-AE Cryptographic Cores prevent against the leakage of secret cryptographic key material through attacks whe...
2988
0.0
AES-ECB-CBC-CFB-CTR-GCM 1 Billion Trace DPA Resistant Crypto Accelerator
Rambus Crypto Accelerator AES-AE–Fast Hardware Cores offload compute intensive cryptographic algorithms in SoC’s CPU at 100x performance (when run at ...
2989
0.0
AES-ECB-CBC-CFB-OFB-CTR Crypto Accelerator
The EIP-36 AES Engines implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS) Publ...
2990
0.0
AES-ECB-CBC-CFB-OFB-CTR-GCM-XTS-CCM Crypto Accelerator
The EIP-39 AES Accelerators implement the Advanced Encryption Standard (AES) algorithm, as specified in Federal Information Processing Standard (FIPS)...
2991
0.0
AES-GCM MACsec (IEEE 802.1AE) and FC-SP Cores
Implementation of the new LAN security standard 802.1ae (MACSec) requires the NIST standard AES cipher in the GCM mode for encryption and message auth...
2992
0.0
AES-GCM Multi-channel upto 2Tbps Crypto Accelerator
The EIP-63, high speed AES-GCM engine is a scalable high-performance, multi-channel cryptographic engine that offers AES-GCM operations as well as AES...
2993
0.0
AES-GCM Single-channel Crypto Accelerator
The EIP-61 is the IP for accelerating AES-GCM based cryptographic solutions. Designed for easy integration and very high performance the EIP-61 crypto...
2994
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AES-GCM Single-channel Crypto Accelerator
The EIP-61 is the IP for accelerating AES-GCM based cryptographic solutions. Designed for easy integration and very high performance the EIP-61 crypto...
2995
0.0
AES-GCM-XTS Crypto Accelerator
The EIP-38 - AES/GCM/XTS/LRW Engines are specifically suited for next generation processors deployed in networking and storage appliances that need to...
2996
0.0
VESA DisplayPort 1.4 RX IP Subsystem for Xilinx FPGAs
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2997
0.0
VESA DisplayPort 1.4 Forward Error Correction (FEC) Receiver
The DisplayPort Forward Error Correction (FEC) Receiver IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPo...
2998
0.0
VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA Displa...
2999
0.0
VESA DisplayPort 1.4 Forward Error Correction (FEC) Transmitter
The DisplayPort Forward Error Correction (FEC) Transmitter IP core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA Displa...
3000
0.0
VESA DisplayPort 2.0 FEC RX
The DisplayPort Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPo...