Design & Reuse
5163 IP
3601
0.0
Globalfoundries 22nm MIPI D-PHY Universal Tx-Rx V1.1@1.5GHz
Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on GF 22nm process technology for SoC designs. Arasan’s D-PHY IP is avail...
3602
0.0
Globalfoundries 22nm MIPI D-PHY Universal Tx-Rx V1.2 @ 2.5GHz
Arasan Chip Systems announces the immediate availability of its MIPI D-PHY(SM) Globalfoundries 22nm FinFET process nodes. Arasan's D-PHY Global Foun...
3603
0.0
Clock Delay Monitor IP
Synopsys’ Clock and Delay Monitor (CDM) is a small IP capable of performing on-chip measurements, monitoring, and safety operations. It can be embedde...
3604
0.0
Clock/Data Recovery PLL
The MXL-PLL-CDR is a clock/data recovery PLL implemented using a digital CMOS process. It is highly integrated and require no external components. Dif...
3605
0.0
Alphacore ASIC Design Services
The Alphacore ASIC design team has extensive experience in delivering complete low power, high speed analog mixed signal, imaging, power management, a...
3606
0.0
Ultra Low Power Edge AI Processor
DMP AI processor IP, ZIA™ DV740, is the ultra low power consumption processor IP for Deep Learning on edge side specialized on inference processing. Z...
3607
0.0
Bluetooth 5.2 / 5.1 / 5.0 / 4.2 LE Controller with Link Layer and optional 802.15.4 MAC
Packetcraft's Bluetooth 5.2 / 5.1 / 5.0 / 4.2 Low Energy Controller IP, (PC-BLE-C5.2), is a highly optimized, comprehensive and flexible solution for ...
3608
0.0
Bluetooth 5.x Low Energy (BLE) RF Transceiver
Orca’s ultra-low power Bluetooth low energy RF transceiver and modem is a best-in-class Bluetooth 5 low energy design for battery-powered IoT and M2M ...
3609
0.0
SM3 Crypto Accelerator
The EIP-52 SM3 Engine implements the SM3 hash algorithm. The accelerators include I/O registers, hash calculation cores, message padding logic, and da...
3610
0.0
SM4 Crypto Accelerator
The EIP-12 SM4 Engine implements the SM4 cipher block algorithm. The accelerator includes I/O registers, encryption and decryption cores. Designed for...
3611
0.0
SM4-XTS Crypto Accelerator
The EIP-312 – SM4-XTS Accelerator is specifically suited for next generation processors deployed in networking and storage appliances and SSD controll...
3612
0.0
DMA AXI4-Stream Interface to AXI Memory Map Address Space
Digital Blocks DB-AXI4-STREAM-TO-AXI4-MM-BRIDGE Verilog RTL IP Core accepts AXI4-Stream data and control input, converts the control TID to a AXI4 Mem...
3613
0.0
HMAC Accelerator with SHA-3, SHA-2, SHA-1
The EIP-59 is the IP for accelerating the various single pass HMAC (FIPS-198-1) algorithms using secure hash integrity algorithms like MD5 (RFC1231),...
3614
0.0
CMAC and XCBC AES Core
The CMAC1 core provides implementation of cryptographic hashes AES-CMAC per NIST SP 800-38B and AES-XCBC. The cores utilize “flow-through” design that...
3615
0.0
HMAC-SHA-2 (224/256/384/512) 100 Million Trace DPA Resistant Crypto Accelerato
Rambus DPA Resistant HMAC-SHA-2 Cryptographic Accelerator Cores prevent against the leakage of secret cryptographic key material through attacks when ...
3616
0.0
AMBA AHB Device/Host Bridge
This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices. The bridge supports Hos...
3617
0.0
AMBA AHB to APB Bus Bridge Core
The AHB2APB implements an AHB to APB bus bridge, allowing the connection of peripherals with an APB interface to an AHB bus. The highly-configurable...
3618
0.0
AMBA AHB Verification IP
AMBA AHB VIP can be configured as Master, Slave and AHB bus and allows Module & System level verification. AMBA AHB VIP is a readymade highly configur...
3619
0.0
AMBA AXI 4.0 Verification IP
eInfochips’ AXI 4.0 Verification IP Product is the Industry’s most comprehensive protocol validation solution for predictable verification of AMBA AXI...
3620
0.0
Embedded Memories for GF (55nm, 40nm, 22nm)
Synopsys provides the industry's broadest portfolio of silicon-proven foundation IP, including Memory Compilers, Logic Libraries and General Purpose I...
3621
0.0
Embedded Memories for Intel (16nm, 18A)
Synopsys provides the industry's broadest portfolio of silicon-proven foundation IP, including Memory Compilers, Logic Libraries and General Purpose I...
3622
0.0
Embedded Memories for SMIC (65nm, 40nm)
Synopsys provides the industry's broadest portfolio of silicon-proven foundation IP, including Memory Compilers, Logic Libraries and General Purpose I...
3623
0.0
Embedded Memories for TSMC (65nm, 40nm, 28nm, 22nm, 16nm, N7, N4, N3)
Synopsys provides the industry's broadest portfolio of silicon-proven foundation IP, including Memory Compilers, Logic Libraries and General Purpose I...
3624
0.0
Embedded Memories for UMC (40nm, 28nm)
Synopsys provides the industry's broadest portfolio of silicon-proven foundation IP, including Memory Compilers, Logic Libraries and General Purpose I...
3625
0.0
UMC L110AELL 110nm Clock Generator PLL - 120MHz-600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
3626
0.0
UMC L110AELL 110nm Clock Generator PLL - 30MHz-150MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
3627
0.0
UMC L110AELL 110nm Clock Generator PLL - 60MHz-300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
3628
0.0
UMC L110AELL 110nm DDR DLL - 24MHz-120MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
3629
0.0
UMC L110AELL 110nm DDR DLL - 32MHz-160MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
3630
0.0
UMC L110AELL 110nm Deskew PLL - 120MHz-600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3631
0.0
UMC L110AELL 110nm Deskew PLL - 30MHz-150MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3632
0.0
UMC L110AELL 110nm Deskew PLL - 60MHz-300MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3633
0.0
UMC L110AELL 110nm Spread Spectrum PLL - 120MHz-600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
3634
0.0
UMC L110AELL 110nm Spread Spectrum PLL - 30MHz-150MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
3635
0.0
UMC L110AELL 110nm Spread Spectrum PLL - 60MHz-300MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
3636
0.0
UMC L110HS 110nm Clock Generator PLL - 160MHz-800MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
3637
0.0
UMC L110HS 110nm Clock Generator PLL - 320MHz-1600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
3638
0.0
UMC L110HS 110nm Clock Generator PLL - 80MHz-400MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
3639
0.0
UMC L110HS 110nm DDR DLL - 104MHz-520MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
3640
0.0
UMC L110HS 110nm DDR DLL - 78MHz-390MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...
3641
0.0
UMC L110HS 110nm Deskew PLL - 160MHz-800MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3642
0.0
UMC L110HS 110nm Deskew PLL - 320MHz-1600MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3643
0.0
UMC L110HS 110nm Deskew PLL - 80MHz-400MHz
The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...
3644
0.0
UMC L110HS 110nm Spread Spectrum PLL - 160MHz-800MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
3645
0.0
UMC L110HS 110nm Spread Spectrum PLL - 320MHz-1600MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
3646
0.0
UMC L110HS 110nm Spread Spectrum PLL - 80MHz-400MHz
The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...
3647
0.0
UMC L110LL 110nm Clock Generator PLL - 120MHz-600MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
3648
0.0
UMC L110LL 110nm Clock Generator PLL - 30MHz-150MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
3649
0.0
UMC L110LL 110nm Clock Generator PLL - 60MHz-300MHz
The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...
3650
0.0
UMC L110LL 110nm DDR DLL - 24MHz-120MHz
The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...