601 10.0

Digital Physical Unclonable Function (PUF) IP Our Digital PUF IP is a digital version of our quantum-based PUF IP (see QDID). The Logic-based Digital PUF IP is a strong hardware root-of-trust for ...

602 10.0

MIPI DSI-2 Transmitter Interface IP MIPI DSI-2 (Display Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile dev...

603 10.0

MIPI I3C Controller and Target fully featured IP solution The MIPI I3C Controller IP is a highly optimized and technology-agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both ASIC and F...

604 10.0

Direct Memory Access DMA Controller IP Core The DMA_CTRL core implements a low-power, single-channel Direct Memory Access (DMA) controller that is used to transfer data across a bus to and from ...

605 10.0

Visibility Improver IP “LucidEye” improves the visibility of unclear images such as those deteriorated due to weather conditions (snow, haze, or fog), and dark images due t...

606 10.0

KiviPQC-Box | Post-Quantum Cryptography (PQC) - Key Encapsulation and Digital Signature IP Core (ML-KEM & ML-DSA) The KiviPQC-Box is an IP core that combines the algorithms ML-DSA and ML-KEM into one single package. ML-DSA and ML-KEM are algorithms that are standa...

607 10.0

KiviPQC-DSA | Post-Quantum Cryptography (PQC) - Digital Signature IP Core (ML-DSA) The KiviPQC-DSA is an IP core implementing the ML-DSA (Module-Lattice-based Digital Signature Algorithm) a post-quantum cryptographic standard defined...

608 10.0

KiviPQC-KEM | Post-Quantum Cryptography (PQC) - Key Encapsulation IP Core (ML-KEM) The KiviPQC-KEM is an IP core implementing the ML-KEM (Module-Lattice-based Key Encapsulation Mechanism) a post-quantum cryptographic standard defined...

609 10.0

4Kx16 Bits OTP (One-Time Programmable) IP, UM- 110 nm 1.2V/3.3V L110AE Process The AT4K16U110MAE0DA is organized as a 4K-bits by 16 one-time programmable memory. This is a kind of non-volatile memory fabricated in UM- L110AE proc...

610 10.0

4Kx32 Bits OTP (One-Time Programmable) IP, TSM- 40nm ULP 1.1V/2.5V Process The AT4K32T40ULP7ZC is organized as 4K-bits by 32 one-time programmable (OTP). This is a type of non-volatile memory fabricated in TSM- 40nm ULP stand...

611 10.0

4Kx8 Bits OTP (One-Time Programmable) IP, GLOBA-FOUNDR---® 22nm FDX 0.8V/1.8V Process The AT4K8G22FDX0AA is organized as a 4K-bits by 8 one-time programmable memory. This is a kind of non-volatile memory fabricated in GLOBA-FOUNDR---® ...

612 10.0

8Kx8 Bits OTP (One-Time Programmable) IP, VI- 0.15µm 1.8V/5V BCD GIII Process The AT8K8V150BCD0DB is organized as an 8K-bit by 8 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in VI- 0.15μm BCD GII...

613 10.0

UniPro 1.6 Host/Device IP The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...

614 10.0

UniPro 1.8 Host/Device IP The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...

615 10.0

UniPro 1.8 Host/Device IP The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...

616 10.0

UniPro Controller 2.0 IP (host / device) The Unified Protocol (UniPro) provides a layered protocol similar to the ISO OSI model. It is designed for high-speed, stable data transfer in mobile ...

617 10.0

Motion JPEG Over IP : HD Video Compression Encoder Subsystem This Video Over IP Subsystem employs JPEG compression and RTP/UDP/IP encapsulation to enable the rapid development of complete motion JPEG video strea...

618 10.0

NR-5G Polar Decoder and Encoder IP Core The Forward Error Correction (FEC) sub-system is one of the essential basing blocks in any communication systems so a powerful FEC code is needed. The...

619 10.0

USB 3.2 Gen2/Gen1 PHY IP in TSMC(3nm, 5nm, 6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm) M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a complete range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps. It is compl...

620 10.0

TSMC DDR3/4 & LPDDR3/4 Combo IP with AXI and DFI 4.0 Interface This DDR3/4 and LPDDR3/4 IP combo solution integrates both controller and PHY, designed for TSMC 22nm process. It offers high-performance data rates u...

621 10.0

TSMC DDR3/4 & LPDDR3/4/4x Combo IP with Controller + PHY This combo IP solution supports DDR3/DDR4 and LPDDR3/LPDDR4/LPDDR4x memory standards, designed for high performance and low power applications on TSMC...

622 10.0

eTCAM (Embedded Ternary Content Addressable Memory IP TCAM can search for data that matches the input in one cycle from all the information stored in the memory.If there are multiple matching data, it is ...

623 10.0

eTCAM (Embedded Ternary Content Addressable Memory IP TCAM can search for data that matches the input in one cycle from all the information stored in the memory.If there are multiple matching data, it is ...

624 10.0

Ethernet IPSec/MACSec Switch/Router IP Core - Efficient and Massively Customizable Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide...

625 10.0

Ethernet Switch / Router IP Core - Efficient and Massively Customizable Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide...

626 10.0

Ethernet TSN Switch IP Core - Efficient and Massively Customizable Packet Architects offers a series of high speed switching/routing IP cores developed using the unique FlexSwitch tool-chain. This allows us to provide...

627 10.0

Multi Protocol Endpoint IP Core for Safe and Secure Ethernet Network "The CetraC EndSystem IP coreis the ideal solution to link your Avionic Computer System to a safe & secure embedded network as ARINC664p7, TSN or Safe...

628 10.0

Multi Protocol IO Concentrator (RDC) IP Core for Safe and Secure Ethernet Network Our IP Core is the ideal solution to link all your equipment, sensor or actuator whatever the used protocol to an Avionic network in a safe & secure m...

629 10.0

Automotive MIPI A-PHY Sink IP (2-Lane) The CL12912IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...

630 10.0

Automotive MIPI A-PHY Sink IP (2-Lane) The CL12912IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...

631 10.0

Automotive MIPI A-PHY Source IP - 1-Lane The CL12911IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...

632 10.0

Automotive MIPI A-PHY Source IP - 1-Lane The CL12911IP4000 is based on MIPI A-PHY interface specification announced in year 2020, targeting ultra-high-speed networking applications in ADAS an...

633 10.0

DVB-S2 Modulator IP Core DVBS2_TX.vhd is the transmitter top level component. Inputs consist of one or several streams (transport, generic). The output is a DDR complex baseba...

634 10.0

DVB-S2X Demodulator ASIC silicon proven IP Core ...

635 10.0

1x64 Bits OTP (One-Time Programmable) IP, Globa-Foundr--- 22nmFDX 0.8V/1.8V Process The AT1X64G22FDX0AA is organized as a 1 by 64 one-time programmable (OTP). This is a kind of non-volatile memory fabricated in Globa-Foundr--- 22nm FD...

636 9.0

Camera High Dynamic Range IP - PINE The PINE with HDR functionality receives a fused Multi-exp. image from the sensor and processes it internally to extend the Dynamic Range of the image...

637 9.0

MIL-STD-1553 IP core MIL-STD-1553B IP Core implements MIL-STD?1553B standard and provides single or multi?functional interface between host processor and MIL-STD-1553 bus ...

638 9.0

ARINC664 End System IP Core ARINC664 End System IP is an IP Core that implements ARINC664 part 7 and provides interface between aircraft LRUs and ARINC664 network. As an implemen...

639 8.0

Camera 3DNR IP - AMUR (ME based) AMUR is a 3D Noise Reduction (3DNR) IP that effectively reduces noise in digital images. It is optimized for low light environment. AMUR uses Motion E...

640 8.0

Camera 3DNR IP - VINI (MA based) VINI is a 3D Noise Reduction (3DNR) IP that effectively reduces noise in digital images. It realizes high performance with low gate size and memory us...

641 8.0

2D/3D OpenGL ES 2.0 vector graphics IP core - D/AVE NX D/AVE NX is the latest and most powerful addition to the D/AVE family of rendering cores. It is the first IP to bring 2D and 3D OpenGL ES 2.0 vector g...

642 8.0

MIPI I3C Verification IP with IBI feature enabled The Maxvy's MIPI-I3C VIP provides configurable option to select I3C master/secondary master/slave based on the MIPI I3C DUT function as per user speci...

643 8.0

Universal Chiplet Interconnect Express (UCIe) Verification IP MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of you...

644 8.0

PRACH IP Suite Optimize your 5G NR O-RAN Split 7.2X design with EIC cutting-edge PRACH Design and Verification Suite. This comprehensive suite includes an end-to-end...

645 8.0

ARINC 429 IP Core ARINC 429 IP Core implements ARINC 429 standard. IP Core contains Rx and Tx processing blocks, Controller Block, Internal Memory and External Memory I...

646 8.0

ARINC 429 IP Core ARINC 429 IP Core implements ARINC 429 standard. IP Core contains Rx and Tx processing blocks, Controller Block, Internal Memory and External Memory I...

647 8.0

TSMC CLN7FF HBM2E PHY IP This datasheet describes GUC HBM (High Bandwidth Memory) PHY IP, which could be integrated with HBM memory controller to provide HBM functionality. Th...

648 8.0

Sub-GHz 433, 868, 915MHz IEEE 802.15.4 RF Transceiver IP The ShortLink Sub-GHz Transceiver RF IP 'SL40LP_Sub1GHzTrx_1' is a complete mixed signal RF IP for the 433, 868 and 915MHz frequency bands. It is comp...

649 7.5

LCD Panel Controller IP (Exclusively for Turnkey ASIC design; not for standalone licensing) This is an LCD Panel Controller IP that can drives multiple LCD panels available in the market. It is configurable to support 1/3-bias, 1/2 bias LCDs....

650 7.5

Temperature Sensor IP (Exclusively for Turnkey ASIC design; not for standalone licensing) This is a Temperature Sensor IP. It measures temperature variations within the IC and converts them in to digital form. The processor in the system ca...