2451 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 55nm LP process UMC 55nm LP/HVT Low-K Logic process 7-Track POWERSLASH Cell Library....

2452 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 7 tracks, UMC 55nm SP process UMC 55nm SP/HVT Logic process 7-Track POWERSLASH Cell Library....

2453 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 8 tracks, UMC 55nm LP process UMC 55nm LP/HVT Low-K Logic process 8-Track POWERSLASH Core Cell Library....

2454 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 8 tracks, UMC 55nm SP process UMC 55nm SP/HVT Low-K process POWERSLASH Cell Library....

2455 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 9 tracks, UMC 28nm HLP process UMC 28nm HLP/HVT Logic process 9-Track POWERSLASH Core Core Cell Library....

2456 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, 9 tracks, UMC 40nm LP process UMC 40nm LP/HVT Logic process 9-Track Standard Cell Library (POWERSLASH Core)....

2457 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm LL process UMC 65nm LL/HVT Low-K Logic process POWERSLASH Core Cell Library....

2458 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, UMC 65nm SP process UMC 65nm SP/HVT process POWERSLASH Cell Library....

2459 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm LL process UMC 90nm LL/HVT Low-K Logic process Cell Library POWERSLASH Core Cell Library (high density Version)....

2460 0.118

Standard Cell PowerSlash(TM) Library IP, HVT, UMC 90nm SP process UMC 90nm SP/HVT Low-K process POWERSLASH Core Cell Library libary....

2461 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 28nm HLP process UMC 28nm Logic and Mixed-Mode HLP/LVT process 12-Track POWERSLASH Cell Library (C35)....

2462 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 40nm LP process UMC 40nm LP/LVT Logic process 12-Track high speed POWERSLASH Core Cell Library....

2463 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 12 tracks, UMC 55nm LP process UMC 55nm LP/LVT Low-K Logic process 12-Track POWERSLASH Core Cell Library....

2464 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library....

2465 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LMINUS (C30)....

2466 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Generic Core Cell Library wtih LPLUS (C38)....

2467 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 28nm HPC process UMC 28nm HPC/LVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library (C35)....

2468 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 40nm LP process UMC 40nm LP/LVT Low-K Logic process 7-Track POWERSLASH Cell Library....

2469 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 7 tracks, UMC 55nm LP process UMC 55nm LP/LVT Low-K Logic process 7-Track POWERSLASH Core Cell Library....

2470 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 8 tracks, UMC 55nm LP process UMC 55nm LP/LVT Low-K Logic process 8-Track POWERSLASH Core Cell Library....

2471 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 9 tracks, UMC 28nm HLP process UMC 28nm HLP/LVT Logic process 9-Track POWERSLASH standard Core Cell Library (C35)....

2472 0.118

Standard Cell PowerSlash(TM) Library IP, LVT, 9 tracks, UMC 40nm LP process UMC 40nm LP/LVT Logic process 9-Track Standard Cell Library (POWERSLASH Core)....

2473 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 28nm HLP process UMC 28nm Logic and Mixed-Mode HLP/RVT process 12-Track Standard POWERSLASH Core Cell Library (C35)....

2474 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 40nm LP process UMC 40nm LP/RVT Logic process 12-Track high speed POWERSLASH Cell Library (C40)....

2475 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 12 tracks, UMC 55nm LP process UMC 55nm LP/RVT Low-K Logic process 12-Track POWERSLASH Core Cell Library....

2476 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library....

2477 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LMINUS (C30 RVT)....

2478 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HLP process UMC 28nm HLP/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library with LPLUS (C38)....

2479 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 28nm HPC process UMC 28nm HPC/RVT Logic and Mixed-Mode process 7-Track POWERSLASH Cell Library (C35)....

2480 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 40nm LP process UMC 40nm LP/RVT Low-K Logic process 7-Track POWERSLASH Cell Library....

2481 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm LP process UMC 55nm LP/RVT Low-K Logic process 7-Track POWERSLASH Core Cell Library....

2482 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 7 tracks, UMC 55nm SP process UMC 55nm SP/RVT Logic process 7-Track POWERSLASH Cell Library....

2483 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 8 tracks, UMC 55nm LP process UMC 55nm LP/RVT Low-K Logic process 8-Track POWERSLASH Core Cell Library....

2484 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 9 tracks, UMC 28nm HLP process UMC 28nm Logic and Mixed-Mode HLP/RVT process 9-Track POWERSLASH Cell Library (C35)....

2485 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, 9 tracks, UMC 40nm LP process UMC 40nm LP/RVT Logic process 9-Track Standard Cell Library (POWERSLASH Core)....

2486 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process UMC 55nm SP/RVT Low-K Logic process UHS Library POWERSLASH cells....

2487 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 55nm SP process UMC 55nm SP/RVT Low-K Logic process Powerlash Core Cell Library....

2488 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm LL process UMC 65nm LL/RVT Low-K process Mini-Library POWERSLASHKit....

2489 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 65nm SP process UMC 65nm SP/RVT Low-K Logic process Powerlash Core Cell Library....

2490 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm LL process UMC 90nm LL/RVT Low-K process Low Power POWERSLASH Core Cell Library....

2491 0.118

Standard Cell PowerSlash(TM) Library IP, RVT, UMC 90nm SP process UMC 90nm SP/RVT Low-K process Low Power standard Cell Library....

2492 0.118

Standard Cell PowerSlash(TM) Library IP, UMC 0.11um LL/FSG process UMC 0.11um LL/FSG Logic process high density POWERSLASH Core Cell Library....

2493 0.118

Standard Cell PowerSlash(TM) Library IP, UMC 0.13um HS/FSG process UMC 0.13um HS/FSG process FSC0H_J POWERSLASHKit core Library....

2494 0.118

Standard Cell PowerSlash(TM) Library IP, UMC 0.13um LL/FSG process UMC 0.13um LL FSG Logic process high density POWERSLASH Core Cell Library....

2495 0.118

Standard Cell PowerSlash(TM) Library IP, UMC 0.13um SP/FSG process UMC 0.13um SP FSG Logic process high density POWERSLASH Core Cell Library....

2496 0.118

Ethernet MAC IP, 10/100 Ethernet MAC, Soft IP 10/100 Ethernet MAC with MII or RMII (Reduced MII) interface....

2497 0.118

Ethernet MAC IP, 10/100/1G Ethernet MAC, DMA (Direct Memory Access) function embedded, Soft IP 10/100/1000 Ethernet Controller with AHB bus....

2498 0.118

FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer rate. This IP is compliant with the V-By-One HS Standard, Ver. 1.3. It transfers the packed packet from direct the video stream FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer rate. This IP is compli...

2499 0.118

Dual Port SRAM Compiler IP, High density, (2RW), UMC 0.13um HS/FSG process UMC 0.13um HS/FSG Logic process high density synchronous Dual Port (2RW) SRAM memory compiler....

2500 0.118

Dual Port SRAM Compiler IP, Output: 1.8432MHz, UMC 40nm LP process UMC 40nm LP Logic process synchronous high density Dual Port SRAM memory compiler....