Cybertek Solution Inc. IP Cores

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1701

1.0

UMC L130LL 130nm Clock Generator PLL - 30MHz-150MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1702

1.0

UMC L130LL 130nm Clock Generator PLL - 60MHz-300MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1703

1.0

UMC L130LL 130nm DDR DLL - 24MHz-120MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1704

1.0

UMC L130LL 130nm DDR DLL - 32MHz-160MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1705

1.0

UMC L130LL 130nm Deskew PLL - 120MHz-600MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1706

1.0

UMC L130LL 130nm Deskew PLL - 30MHz-150MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1707

1.0

UMC L130LL 130nm Deskew PLL - 60MHz-300MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1708

1.0

UMC L130LL 130nm Spread Spectrum PLL - 120MHz-600MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1709

1.0

UMC L130LL 130nm Spread Spectrum PLL - 30MHz-150MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1710

1.0

UMC L130LL 130nm Spread Spectrum PLL - 60MHz-300MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1711

1.0

UMC L130SP 130nm Clock Generator PLL - 118MHz-590MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1712

1.0

UMC L130SP 130nm Clock Generator PLL - 236MHz-1180MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1713

1.0

UMC L130SP 130nm Clock Generator PLL - 59MHz-295MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1714

1.0

UMC L130SP 130nm DDR DLL - 57MHz-285MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1715

1.0

UMC L130SP 130nm DDR DLL - 76MHz-380MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1716

1.0

UMC L130SP 130nm Deskew PLL - 118MHz-590MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1717

1.0

UMC L130SP 130nm Deskew PLL - 236MHz-1180MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1718

1.0

UMC L130SP 130nm Deskew PLL - 59MHz-295MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1719

1.0

UMC L130SP 130nm Spread Spectrum PLL - 118MHz-590MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1720

1.0

UMC L130SP 130nm Spread Spectrum PLL - 236MHz-1180MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1721

1.0

UMC L130SP 130nm Spread Spectrum PLL - 59MHz-295MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1722

1.0

UMC L150HS 150nm Clock Generator PLL - 140MHz-700MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1723

1.0

UMC L150HS 150nm Clock Generator PLL - 280MHz-1400MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1724

1.0

UMC L150HS 150nm Clock Generator PLL - 70MHz-350MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1725

1.0

UMC L150HS 150nm DDR DLL - 57MHz-285MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1726

1.0

UMC L150HS 150nm DDR DLL - 76MHz-380MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1727

1.0

UMC L150HS 150nm Deskew PLL - 140MHz-700MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1728

1.0

UMC L150HS 150nm Deskew PLL - 280MHz-1400MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1729

1.0

UMC L150HS 150nm Deskew PLL - 70MHz-350MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1730

1.0

UMC L150HS 150nm Spread Spectrum PLL - 140MHz-700MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1731

1.0

UMC L150HS 150nm Spread Spectrum PLL - 280MHz-1400MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1732

1.0

UMC L150HS 150nm Spread Spectrum PLL - 70MHz-350MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1733

1.0

UMC L180G 180nm Clock Generator PLL - 100MHz-500MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1734

1.0

UMC L180G 180nm Clock Generator PLL - 200MHz-1000MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1735

1.0

UMC L180G 180nm Clock Generator PLL - 50MHz-250MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1736

1.0

UMC L180G 180nm DDR DLL - 42MHz-210MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1737

1.0

UMC L180G 180nm DDR DLL - 56MHz-280MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1738

1.0

UMC L180G 180nm Deskew PLL - 100MHz-500MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1739

1.0

UMC L180G 180nm Deskew PLL - 200MHz-1000MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1740

1.0

UMC L180G 180nm Deskew PLL - 50MHz-250MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1741

1.0

UMC L180G 180nm Spread Spectrum PLL - 100MHz-500MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1742

1.0

UMC L180G 180nm Spread Spectrum PLL - 200MHz-1000MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1743

1.0

UMC L180G 180nm Spread Spectrum PLL - 50MHz-250MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1744

1.0

UMC L55SP 55nm Clock Generator PLL - 130MHz-650MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1745

1.0

UMC L55SP 55nm Clock Generator PLL - 260MHz-1300MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1746

1.0

UMC L55SP 55nm Clock Generator PLL - 520MHz-2600MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1747

1.0

UMC L55SP 55nm DDR DLL - 150MHz-750MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1748

1.0

UMC L55SP 55nm DDR DLL - 200MHz-1000MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1749

1.0

UMC L55SP 55nm DDR DLL - 316MHz-1580MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1750

1.0

UMC L55SP 55nm Deskew PLL - 130MHz-650MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

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