Cybertek Solution Inc. IP Cores

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1801

1.0

USB 3.0 SSIC PHY

The Arasan Superspeed Inter-chip Controller (USB 3.0 SSIC Adapter) uses Arasan’s MIPI-M-PHY (Type-1) v. 3.0 to implement the SSIC adaptation to the US...

1802

1.0

USB HSIC PHY - High Speed Inter-Chip IP Core

USB is the ubiquitous peripherals interconnect of choice for large number of computing and consumer applications. Many systems provide a comprehensive...

1803

1.0

TSMC CL013G 130nm Clock Generator PLL - 136MHz-680MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1804

1.0

TSMC CL013G 130nm Clock Generator PLL - 272MHz-1360MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1805

1.0

TSMC CL013G 130nm Clock Generator PLL - 68MHz-340MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1806

1.0

TSMC CL013G 130nm DDR DLL - 107MHz-535MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1807

1.0

TSMC CL013G 130nm DDR DLL - 51MHz-255MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1808

1.0

TSMC CL013G 130nm DDR DLL - 68MHz-340MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1809

1.0

TSMC CL013G 130nm Deskew PLL - 136MHz-680MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1810

1.0

TSMC CL013G 130nm Deskew PLL - 272MHz-1360MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1811

1.0

TSMC CL013G 130nm Deskew PLL - 68MHz-340MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1812

1.0

TSMC CL013G 130nm General Purpose PLL - 136MHz-680MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

1813

1.0

TSMC CL013G 130nm Spread Spectrum PLL - 136MHz-680MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1814

1.0

TSMC CL013G 130nm Spread Spectrum PLL - 272MHz-1360MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1815

1.0

TSMC CL013G 130nm Spread Spectrum PLL - 68MHz-340MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1816

1.0

TSMC CL013LP 130nm Clock Generator PLL - 110MHz-550MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1817

1.0

TSMC CL013LP 130nm Clock Generator PLL - 220MHz-1100MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1818

1.0

TSMC CL013LP 130nm Clock Generator PLL - 55MHz-275MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1819

1.0

TSMC CL013LP 130nm DDR DLL - 42MHz-210MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1820

1.0

TSMC CL013LP 130nm DDR DLL - 56MHz-280MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1821

1.0

TSMC CL013LP 130nm DDR DLL - 88MHz-440MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1822

1.0

TSMC CL013LP 130nm Deskew PLL - 110MHz-550MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1823

1.0

TSMC CL013LP 130nm Deskew PLL - 220MHz-1100MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1824

1.0

TSMC CL013LP 130nm Deskew PLL - 55MHz-275MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1825

1.0

TSMC CL013LP 130nm General Purpose PLL - 110MHz-550MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

1826

1.0

TSMC CL013LP 130nm Spread Spectrum PLL - 110MHz-550MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1827

1.0

TSMC CL013LP 130nm Spread Spectrum PLL - 220MHz-1100MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1828

1.0

TSMC CL013LP 130nm Spread Spectrum PLL - 55MHz-275MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1829

1.0

TSMC CL013LV 130nm Clock Generator PLL - 160MHz-800MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1830

1.0

TSMC CL013LV 130nm Clock Generator PLL - 320MHz-1600MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1831

1.0

TSMC CL013LV 130nm Clock Generator PLL - 80MHz-400MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1832

1.0

TSMC CL013LV 130nm DDR DLL - 139MHz-695MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1833

1.0

TSMC CL013LV 130nm DDR DLL - 66MHz-330MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1834

1.0

TSMC CL013LV 130nm DDR DLL - 88MHz-440MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1835

1.0

TSMC CL013LV 130nm Deskew PLL - 160MHz-800MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1836

1.0

TSMC CL013LV 130nm Deskew PLL - 320MHz-1600MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1837

1.0

TSMC CL013LV 130nm Deskew PLL - 80MHz-400MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1838

1.0

TSMC CL013LV 130nm General Purpose PLL - 160MHz-800MHz

The General Purpose PLL is a wide range clock multiplier with deskew capability. It contains a 1-16 divider at the reference clock input, a 1-64 divid...

1839

1.0

TSMC CL013LV 130nm Spread Spectrum PLL - 160MHz-800MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1840

1.0

TSMC CL013LV 130nm Spread Spectrum PLL - 320MHz-1600MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1841

1.0

TSMC CL013LV 130nm Spread Spectrum PLL - 80MHz-400MHz

The Spread Spectrum PLL is designed to multiply an input clock by a fixed-point number between 92 and 184 with frequency spreading capability suitable...

1842

1.0

TSMC CL013LVOD 130nm Clock Generator PLL - 110MHz-550MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1843

1.0

TSMC CL013LVOD 130nm Clock Generator PLL - 220MHz-1100MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1844

1.0

TSMC CL013LVOD 130nm Clock Generator PLL - 440MHz-2200MHz

The Clock Generator PLL is designed to multiply an input clock by an integer between 1 and 4096. It does not provide any deskew functionality. It cont...

1845

1.0

TSMC CL013LVOD 130nm DDR DLL - 116MHz-580MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1846

1.0

TSMC CL013LVOD 130nm DDR DLL - 183MHz-915MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1847

1.0

TSMC CL013LVOD 130nm DDR DLL - 87MHz-435MHz

The DDR DLL uses a reference clock to establish a time base in order to delay arbitrary (nonperiodic) strobe signals by precise fractions of the clock...

1848

1.0

TSMC CL013LVOD 130nm Deskew PLL - 110MHz-550MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1849

1.0

TSMC CL013LVOD 130nm Deskew PLL - 220MHz-1100MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

1850

1.0

TSMC CL013LVOD 130nm Deskew PLL - 440MHz-2200MHz

The Deskew PLL is designed to eliminate the skew between the output of a clock distribution tree and a clock reference. The PLL can also multiply the ...

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