Design & Reuse
Catalog of SIP Cores
System on Chip design resources
5550 IP
251
50.0
AHB Octal SPI Controller with PSRAM and XIP Support
The Silvaco Octal SPI Memory Controller IP core is a serial peripheral interface (SPI) master which controls an external serial device, usually an ind...
252
50.0
PHY for PCIe 5.0 and CXL for Samsung
Cadence 32G NRZ multi-;protocol PHY The Cadence 32G Multi-Protocol PHY IP for Samsung is a high--performance SerDes operating from 1.25Gbps to 32Gb...
253
50.0
PHY for PCIe 5.0 and CXL for TSMC
Cadence 32G NRZ multi-;protocol PHY The Cadence 32G Multi-Protocol PHY IP for TSMC is a high--performance SerDes operating from 1.25Gbps to 32Gbps ...
254
50.0
High Performance DDR5/4/3 Memory Controller
Mobiveil's DDR5/4/3 Memory Controller is a highly flexible and configurable design targeted for high performance enterprise server and real-time consu...
255
50.0
MIPI C-PHY v1.0 D-PHY v1.2 TX 2 trios/2 Lanes in TSMC (12nm, N5, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
256
50.0
MIPI C-PHY v1.0 D-PHY v1.2 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
257
50.0
MIPI C-PHY v1.2 D-PHY v2.1 TX 3 trios/4 Lanes in TSMC (16nm, 12nm, N7, N6, N5, N4, N4P, N3E, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
258
50.0
MIPI C-PHY v2.0 D-PHY v2.1 RX 2 trios/2 Lanes in TSMC (N7, N6, N5, N4, N4C, N3E, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
259
50.0
MIPI C-PHY v2.0 D-PHY v2.1 RX 3 trios/4 Lanes in TSMC (N6, N6C, N5, N4P, N4C, N3P)
Synopsys’ integrated C-PHY/D-PHY IP enables high-performance, low-power interface to SoCs, application processors, baseband processors, and peripheral...
260
50.0
MIPI D-PHY Universal Tx / Rx v1.1 @1.5ghz Ultra Low Power for IoT & Wearables
Arasan 2nd Generation MIPI D-PHY v1.1 IP supporting speeds of up to 1.5 Gbps on TSMC 22nm process technology for SoC designs. Arasan’s D-PHY IP is ava...
261
50.0
MIPI DSI-2 Receiver Controller v1.0
The Arasan DSI-2 Device Controller IP is designed to provide MIPI DSI-2 1.0 compliant high speed serial connectivity for mobile display modules with T...
262
50.0
MIPI I3C PHY - TSMC (12nm, 7nm, 5nm, and 22nm) - GF 12nm
The I3C bus (incl. PHY) is used for various sensors in the mobile/automotive system where the Host transfers data and control between itself and vario...
263
50.0
MIPI M-PHY - TSMC 40nm
MIPI M-PHY Specification Version 3.0 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabilities. A M-PHY config...
264
50.0
MIPI M-PHY G4 Type 1 2Tx2RX in TSMC (16nm, 12nm, N7, N6, N5, N4, N3A, N3E)
The silicon-proven Synopsys MIPI® M-PHY IP, compliant with the latest MIPI M-PHY v5.0 specification, supports speeds up to 23.32 Gbps per lane. The I...
265
50.0
Ultra High-Speed Cache Memory Compiler
Silvaco’s Ultra High-Speed cache memory is an adaptable, independent, non-coherent cache Intellectual Property (IP) featuring an advanced cache ar...
266
50.0
ONFI 3.2 NV-DDR2 PHY in GDSII
Compliant to ONFI 3.2 electrical interface, Arasan ONFI 3.2 PHY, delivered in hard macro, is process technology proven and easy to integrate. This ON...
267
50.0
ONFI 4.0 NAND Flash Controller & PHY
The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP is changing with it. New applications are emerging and innovative IP solu...
268
50.0
ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 12nm
The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP Core is changing in accordance with it. New applications are emerging and...
269
50.0
ONFI 4.1 NAND Flash Controller & PHY & IO Pads on 28nm
The NAND Flash landscape is changing and the Arasan NAND Flash Controller IP Core is changing in accordance with it. New applications are emerging and...
270
50.0
Modern, high performance Audio DSP, optimized for far-field noise reduction and Artificial Intelligence speech recognition
The Ceva-BX2 audio/voice DSP is targeted for high performance audio devices such as DTV, Smart Speaker, Soundbar, and car infotainment systems. Ceva-...
271
50.0
Low-power, high-speed 12-bit 4GSPS SAR (ADC) TSMC 28nm HPC+
The A12B4G is a low-power, high-speed analog to digital converter (ADC) intellectually property (IP) design block. It is a time interleaved (TI) succe...
272
50.0
Low-power, high-speed 12-bit, 8 GSPS Analog to Digital Converter (ADC) IP block TSMC 28nm HPC+ process
The A12B8G is a low-power, high-speed analog to digital converter (ADC) intellectually property (IP) design block. It is a time interleaved (TI) succe...
273
50.0
LPDDR5X/5/4X PHY in TSMC (N5, N4P, N4C, N3E, N3P, N3A)
The Synopsys LPDDR5X/5/4X PHY is Synopsys’ physical (PHY) layer IP interface solution for ASICs, ASSPs, system-on-chips (SoCs) and system- in- package...
274
50.0
Open RAN Platform for Base Station and Radio
Industry’s First Comprehensive 5G Baseband Platform IP for 5G RAN ASICs and Open RAN Building on more than a decade of leadership in baseband IP solut...
275
50.0
USB 2.0 nanoPHY in SMIC (65nm)
The Synopsys USB 2.0 nanoPHY provides designers with a complete Physical Layer (PHY) IP solution, designed for low-power mobile and consumer applicati...
276
50.0
USB 3.1 PHY (10G/5G) inTSMC (16nm, 12nm, N7, N6, N5,N3E, N3P)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...
277
50.0
USB-C 3.1 DP/TX PHY ebdaux in TSMC (N6C, N5, N4P, N4C, N3E)
The Synopsys SuperSpeed 3.1 USB IP solution is based on the USB 3.0 specification from the USB Implementer Forum. The comprehensive USB 3.1 IP offerin...
278
50.0
USB-C 3.2 DP/TX PHY in TSMC (N3P)
The Synopsys USB-C 3.2/DisplayPort 1.4 IP solution consists of USB-C 3.2/DisplayPort 1.4 PHYs, USB-C 3.2/DisplayPort 1.4 controllers (Device, Host, or...
279
50.0
USB-C 3.2 SS/SSP PHY in Type-C in TSMC (N7, N6, N5, N3E)
The Synopsys SuperSpeed 3.2 USB IP solution is based on the USB 3.2 specification from the USB Implementer Forum. The USB 3.2 IP offering includes con...
280
50.0
TSMC 3nm (N3E) 1.2V LVDS
Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...
281
50.0
TSMC 3nm (N3E) 1.2V/1.8V GPIO Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
282
50.0
TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
283
50.0
TSMC 3nm (N3E) 1.2V/1.8V GPIO with 1.8V Failsafe Libraries, multiple metalstacks
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
284
50.0
TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries
Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...
285
50.0
TSMC 3nm (N3E) 1.2V/1.8V I3C Libraries, multiple metalstacks
Synopsys I3C I/O library supports a simplified system of connecting and managing multiple sensors in a device. Multiple sensor secondary devices can b...
286
50.0
TSMC 3nm (N3E) 1.5V LVDS
Synopsys Low Voltage Differential Signaling (LVDS) I/O library is a high-frequency interface that uses differential signals for data transmission. A f...
287
50.0
TSMC 3nm (N3E) 1.8V SD/eMMC IO
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...
288
50.0
TSMC 3nm (N3E) 1.8V SD/eMMC PHY
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...
289
50.0
TSMC 3nm (N3E) 1.8V SD/eMMC PHY, multiple metalstacks
Synopsys SD/eMMC PHY provides an optimal balance for cost and performance for storage solutions. Synopsys SD/eMMC PHY is a hard IP that can be used to...
290
50.0
TSMC 3nm (N3E) GPIO Basekit Libraries
Synopsys’ General-Purpose I/O (GPIO) Library IP provides designers with the input/output operation, functionality, and reliability required for their ...
291
50.0
Quad SPI Controller
The Serial Peripheral Interface or SPI-bus is a simple 4- wire serial communications interface used by many peripheral chips that enable the controlle...
292
50.0
Multi-protocol wireless plaform integrating 802.11ax (Wi-Fi 6), Bluetooth 5.4 Dual Mode, 802.15.4 (for Thread, Zigbee and Matter)
Ceva-Waves Links is a versatile family of multi-protocol wireless platform IPs, encompassing the latest consumer wireless standards. It leverages the ...
293
50.0
Hyperbus Flash Memory Controller
Emerging high-performance applications demand increasingly fast read throughputs from NOR-flash memory devices. At the same time, the pin-count requir...
294
46.0
32Gbps, 31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 31 order, up to 32Gbps. Error count is accurate: no double counts or omissions reg...
295
46.0
32Gbps, 7/15 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7 or 15 order, up to 32Gbps. Error count is accurate: no double counts or omission...
296
46.0
32Gbps, 7/15/31 order, Pseudo Random Bit Sequence Generator, Checker, Error Counter
This unit generates and checks Pseudo Random Bit Sequence (PRBS) of 7, 15 or 31 order, up to 32Gbps. Error count is accurate: no double counts or omis...
297
40.0
16-Bit xSPI PSRAM Master
Arasan Chip System’s PSRAM x16 master IP is easy to use, simple to work with, quick to operate, and reliable under all conditions. It supports newer 1...
298
40.0
LDPC Decoder for 5G NR and Wireless
Mobiveil's 5G NR LDPC Decoder IP Core offers a robust solution for LDPC decoding, featuring a dedicated LDPC decoder block for optimal performance. It...
299
40.0
VESA DisplayPort DP 1.4a / eDP 1.4b RX PHY , MST
Silicon Library's VESA DP 1.4a / eDP 1.4b RX PHY IP supports 1.62Gbps , 2.7Gbps , 5.4Gbps and 8.1Gbps , depending on the technology node. This silico...
300
40.0
VESA DisplayPort DP 1.4a / eDP 1.4b TX PHY
Silicon Library's VESA DP 1.4 a/ eDP 1.4b TX PHY IP supports 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps, depending on the technology node. This silicon p...